STM32H743VIT6

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1. Description

STM32H742xI/G and STM32H743VIT6 devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H742xI/G and STM32H743xI/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. STM32H742xI/G and STM32H743xI/G devices incorporate high-speed embedded memories with a dual-bank Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

    1. Standard peripherals

        – Four I2Cs

        – Four USARTs, four UARTs and one LPUART

        – Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked by a dedicated internal audio PLL or by an external clock to allow synchronization.

        – Four SAI serial audio interfaces

        – One SPDIFRX interface

        – One SWPMI (Single Wire Protocol Master Interface)

        – Management Data Input/Output (MDIO) slaves

        – Two SDMMC interfaces

        – A USB OTG full-speed and a USB OTG high-speed interface with full-speed capability (with the ULPI)

        – One FDCAN plus one TT-FDCAN interface

        – An Ethernet interface

        – Chrom-ART Accelerator™

        – HDMI-CEC

    2. Advanced peripherals including

        – A flexible memory control (FMC) interface

        – A Quad-SPI Flash memory interface

        – A camera interface for CMOS sensors

        – An LCD-TFT display controller (only available on STM32H743xI/G)

        – A JPEG hardware compressor/decompressor (only available on STM32H743xI/G)

STM32H742xI/G and STM32H743xI/G features and peripheral counts for the list of peripherals available on each part number. STM32H742xI/G and STM32H743xI/G devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor and connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled. Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages except LQFP100 to allow a greater power supply choice. A comprehensive set of power-saving modes allows the design of low-power applications. STM32H742xI/G and STM32H743xI/G devices are offered in 8 packages ranging from 100 pins to 240 pins/balls. The set of included peripherals changes with the device chosen.

2. Features

    1. Core

        - 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

    2. Memories

        - Up to 2 Mbytes of Flash memory with readwhile-write support

        - Up to 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), Up to 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain

        - Dual mode Quad-SPI memory interface running up to 133 MHz

        - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 100 MHz in Synchronous mode

        - CRC calculation unit

    3. Security

        - ROP, PC-ROP, active tamper

    4. General-purpose input/outputs

        - Up to 168 I/O ports with interrupt capability

    5. Reset and power management

        - 3 separate power domains which can be independently clock-gated or switched off:

           – D1: high-performance capabilities

           – D2: communication peripherals and timers

           – D3: reset/clock control/power management

        - 1.62 to 3.6 V application supply and I/Os

        - POR, PDR, PVD and BOR

        - Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs

        - Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry

        - Voltage scaling in Run and Stop mode (6 configurable ranges)

        - Backup regulator (~0.9 V)

        - Voltage reference for analog peripheral/VREF+

        - Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging

    6. Low-power consumption

        - VBAT battery operating mode with charging capability

        - CPU and domain power state monitoring pins

        - 2.95 µA in Standby mode (Backup SRAM OFF,RTC/LSE ON)

    7. Clock management

        - Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI

        - External oscillators: 4-48 MHz HSE, 32.768 kHz LSE

        - 3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode

    8. Interconnect matrix

        - 3 bus matrices (1 AXI and 2 AHB)

        - Bridges (5× AHB2-APB, 2× AXI2-AHB)

    9. 4 DMA controllers to unload the CPU

        - 1× high-speed master direct memory access controller (MDMA) with linked list support

        - 2× dual-port DMAs with FIFO

        - 1× basic DMA with request router capabilities

  10. Up to 35 communication peripherals

        - 4× I2Cs FM+ interfaces (SMBus/PMBus)

        - 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART

        - 6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz)

        - 4x SAIs (serial audio interface)

        - SPDIFRX interface

        - SWPMI single-wire protocol master I/F

        - MDIO Slave interface

        - 2× SD/SDIO/MMC interfaces (up to 125 MHz)

        - 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)

        - 2× USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD

        - Ethernet MAC interface with DMA controller

        - HDMI-CEC

        - 8- to 14-bit camera interface (up to 80 MHz)

  11. 11 analog peripherals

        - 3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS)

        - 1× temperature sensor

        - 2× 12-bit D/A converters (1 MHz)

        - 2× ultra-low-power comparators

        - 2× operational amplifiers (7.3 MHz bandwidth)

        - 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters

  12. Up to 22 timers and watchdogs

        - 1× high-resolution timer (2.1 ns max resolution)

        - 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz)

        - 2× 16-bit advanced motor control timers (up to 240 MHz)

        - 10× 16-bit general-purpose timers (up to 240 MHz)

        - 5× 16-bit low-power timers (up to 240 MHz)

        - 2× watchdogs (independent and window)

        - 1× SysTick timer

        - RTC with sub-second accuracy and hardware calendar

  13. Debug mode

        - SWD & JTAG interfaces

        - 4-Kbyte Embedded Trace Buffer

3. Applications

    1. Motor drive and application control

    2. Medical equipment

    3. Industrial applications: PLC, inverters, circuit breakers

    4. Printers, and scanners

    5. Alarm systems, video intercom, and HVAC

    6. Home audio appliances

    7. Mobile applications, Internet of Things

    8. Wearable devices: smart watches.

4. Functional overview

    1. Arm® Cortex®-M7 with FPU

        The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex®-M7 processor is a highly efficient high-performance featuring:

    - Six-stage dual-issue pipeline

    - Dynamic branch prediction

    - Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)

    - 64-bit AXI interface

    - 64-bit ITCM interface

    - 2x32-bit DTCM interfaces

The following memory interfaces are supported:

    - Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency

    - Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses

    - AXI Bus interface to optimize Burst transfers

    - Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

    2. Memory protection unit (MPU)

        The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated.

    3. Low-power strategy

        There are several ways to reduce power consumption on STM32H742xI/G and STM32H743xI/G:

    1. Decrease the dynamic power consumption by slowing down the system clocks even in Run mode and by individually clock gating the peripherals that are not used.

    2. Save power consumption when the CPU is idle, by selecting among the available lowpower mode according to the user application needs. This allows achieving the best compromise between short startup time, low-power consumption, as well as available wakeup sources.

The devices feature several low-power modes:

       - CSleep (CPU clock stopped)

       - CStop (CPU sub-system clock stopped)

       - DStop (Domain bus matrix clock stopped)

       - Stop (System clock stopped)

       - DStandby (Domain powered down) 

       - Standby (System powered down)

CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex®-Mx core is set after returning from an interrupt service routine. A domain can enter low-power mode (DStop or DStandby) when the processor, its subsystem and the peripherals allocated in the domain enter low-power mode. If part of the domain is not in low-power mode, the domain remains in the current mode. Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains are in DStop or DStandby mode.

    4. Reset and clock controller (RCC)

        The clock and reset controller is located in D3 domain. The RCC manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the baudrate.

    5. General Purpose Input/Output (GPIO)

        Each GPIO pin can be configured as an output (push-pull or open-drain, With or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) Or as a peripheral backup function. Most GPIO pins are shared with digital or analog Alternative function. All GPIOs have high current capability and have speed options to better Manage internal noise, power consumption and electromagnetic radiation. After reset, all GPIOs (except debug pins) are in analog mode to reduce power consumption Consumption. If needed, the I/O configuration can be locked in a specific order so that Avoid false writes to I/O registers.