SY100E310LJI

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The SY100E310LJI is a high-performance and low-jitter clock distribution device that operates from a single-ended LVDS clock source up to a maximum frequency of 1 GHz. The device consists of a set of high-performance clock buffers with an integrated phase-locked loop (PLL) for timing and jitter reduction, enabling the system designer to have a complete clock solution with a single device. The device is designed to deliver buffered and complement clock outputs with signal quality and signal integrity performance similar to differential clocks.

Application Field

The SY100E310LJI is ideal for applications requiring multiple clock distribution with low jitter and signal quality performance, such as data storage, processing and communication systems. The device’s unique configuration, with the integrated PLL, reduces the need of having multiple devices that must communicate with each other. It is also ideal for applications that require low jitter clock generation.

Working Principle

The SY100E310LJI consists of a set of high-performance clock buffers paired with an integrated PLL for timing extraction and jitter reduction from a single-ended LVDS clock source. The timing extraction process starts by the PLL extracting the clock signal from the LVDS source, after which the clock signals are buffered through the high-performance clock buffers. This buffered clock signal is then divided by a selectable divider and routed to the different outputs. The PLL ensures that the jitter of the clock remains low even when the source clock is subjected to variations in terms of frequency and duty cycle.

The clock buffers in the device are configurable to either accept or reject a spread spectrum clock signal. The buffers are provided with a programmable delay line to adjust the timing of the signals routed out of the device. The delay line also provides flexibility to account for timing skew between the clocks generated within the device. The device also consists of adjustable slew settings which can be used to tune the slew rate of the clock signals.

The SY100E310LJI is one of the few devices that require no external power supplies, as it is powered directly by the LVDS clock source. The device is controlled through an I2C interface that can be used to control the device settings and to reprogram various clock settings without having to physically reprogram the device.

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