TDA8950J/N1,112 Allicdata Electronics
Allicdata Part #:

568-4782-5-ND

Manufacturer Part#:

TDA8950J/N1,112

Price: $ 0.00
Product Category:

Integrated Circuits (ICs)

Manufacturer: NXP USA Inc
Short Description: IC AMP AUDIO PWR 340W STER 23SILAmplifier IC 1-Cha...
More Detail: N/A
DataSheet: TDA8950J/N1,112 datasheetTDA8950J/N1,112 Datasheet/PDF
Quantity: 18800
Lead Free Status / RoHS Status: ROHS3 Compliant
Moisture Sensitivity Level (MSL): Not Applicable
Stock 18800Can Ship Immediately
Specifications
Series: TDA8950
Packaging: Tube 
Lead Free Status / RoHS Status: --
Part Status: Active
Moisture Sensitivity Level (MSL): --
Type: Class D
Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
Max Output Power x Channels @ Load: 340W x 1 @ 8 Ohm; 170W x 2 @ 4 Ohm
Voltage - Supply: ±12.5 V ~ 40 V
Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection, Standby
Mounting Type: Through Hole
Operating Temperature: -40°C ~ 85°C (TA)
Supplier Device Package: DBS23P
Package / Case: 23-SIP Formed Leads
Base Part Number: TDA8950
Description

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1. Describe

The TDA8950J/N1,112 is a high-efficiency class-D audio power amplifier. Typical output power is 2 × 150 W with a speaker load impedance of 4 Ω. The TDA8950 is available in HSOP24 and DBS23P power supply packages. The amplifier operates over a wide supply voltage range of ±12.5 V to ±40 V and features low quiescent current consumption.

2. Feature

    1. HSOP24 and DBS23P packages are pin compatible with TDA8920B

    2. Symmetrical operating supply voltage range of ±12.5 V to ±40 V

    3. Stereo fully differential inputs that can be used as stereo single-ended (SE) or mono bridge-tied load (BTL) amplifiers

    4. High output power in typical applications:

        - SE 2 × 150 W, RL = 4 Ω (VP = ±37 V)

        - SE 2 × 170 W, RL = 4 Ω (VP = ±39 V)

        - SE 2 × 100 W, RL = 6 Ω (VP = ±37 V)

        - BTL 1 × 300 W, RL = 8 Ω (VP = ±37 V)

    5. low noise

    6. Smooth pop and noiseless startup and shutdown

    7. Zero dead time switching

    8. Fixed frequency

    9. Internal or external clock

  10. high efficiency

  11. Low quiescent current

  12. Advanced protection strategies: voltage protection and output current limit

  13. Thermal Foldback (TFB)

  14. Fixed gain of 30 dB in SE and 36 dB in BTL applications

  15. Complete load short circuit protection

  16. BD modulation in BTL configuration

3. Application

    1. DVD

    2. Micro and Micro Receivers

    3. Home Theater in a Box (HTIAB) system

    4. High-power speaker system

4. Pin configuration

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5. Pin Description

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6. PWM frequency

The amplifier output signal is a PWM signal with a typical carrier frequency between 250 kHz and 450 kHz. A second-order LC demodulation filter at the output is used to convert the PWM signal to an analog audio signal. The carrier frequency is determined by an external resistor ROSC connected between pins OSC and VSSA. The optimal carrier frequency setting is between 250 kHz and 450 kHz. The carrier frequency is set to 345 kHz by pins OSC and VSSA. If two or more Class D amplifiers are used in the same audio application, it is recommended that all devices use an external clock circuit. This will ensure they operate at the same switching frequency, thus avoiding beat notes

7. Supply voltage protection

If the supply voltage falls below the minimum supply voltage threshold VP(uvp), the UVP circuit will be activated and the system will shut down. Once the supply voltage rises above VP(uvp) again, the system will restart after a 100 ms delay. If the supply voltage exceeds the maximum supply voltage threshold VP(ovp), the OVP The circuit will be activated and the power stage will be turned off. When the supply voltage falls below VP(ovp) again, the system will restart after a delay of 100 ms. An additional unbalance protection (UBP) circuit compares the positive analog supply voltage (on pin VDDA) with the negative analog supply voltage (on pin VSSA) and is Triggers if the voltage difference exceeds twice. When the supply voltage difference is below the unbalance threshold, VP(ubp), the system reboots after 100ms.

8. External clock

To ensure duty cycle independent operation, the external clock frequency is internally divided by two. Therefore, the external clock frequency is twice the internal clock frequency (typically 2 × 350 kHz = 700 kHz). If multiple Class D amplifiers are used in a single application, it is recommended that all devices operate at the same switching frequency. This can be achieved by connecting the OSC pins together and feeding from an external oscillator. when using external oscillator, it is necessary to force pin OSC to a DC level higher than SGND. This disables the internal oscillator and causes the PWM to switch at half the external clock frequency. The internal oscillator requires an external resistor ROSC, connected between pin OSC and pin VSSA. ROSC must be removed when using an external oscillator. The noise generated by the internal oscillator depends on the supply voltage. For low noise applications operating at high supply voltages, an external low noise oscillator is recommended.


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