THC63LVD1024

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1. Describe

The THC63LVD1024 receiver is designed to support Host and tablet dual link transmission Display resolutions up to 1080p/QXGA. this THC63LVD1024 converts the LVDS data stream back to 67-bit CMOS/TTL data with falling edge or rising edge clock, convenient to communicate with various LCDs Panel controller. In Dual Link, the data transmission clock frequency is 135MHz, 67bits RGB data transmission The effective rate of each LVDS channel is 945Mbps. Use one 135MHz clock, data throughput of 1.1Gbytes per second.

2. Feature

    1. Suitable for TV signal (480i1080p), PC signal (VGA-QXGA) wide dot clock range

        - Dual LVDS port input/dual TTL port output mode: 8-135MHz (clock output)

        - Dual LVDS port input/single TTL port output mode: 40-150MHz (clock output)

    2. PLL does not require external components

    3. Flexible input/output mode

       1. Single/dual LVDS port IN/single/dual TTL port OUT

       2. Bilateral output

    4. 50% output clock duty cycle

    5. TTL clock edge selectable

    6. TTL clock output timing is programmable (3 steps)

    7. 2 output data mapping to simplify PCB layout.

    8. Power down mode

    9. 144pin LQFP exposed pad

  10. Compliant with EU RoHS

3. Pin configuration

4. Pin Description