THS788PFDT

THS788PFDT is an integrated PLL clock buffer from Texas Instruments. It operates from 8 kbps up to 10 Gbps. The device can drive differential outputs at up to 400 mV into 28uA for improved signal integrity. It also includes an internal charge pump for wide-range operation.

The purpose of the THS788PFDT device is to reduce jitter and provide a low-power solution for clock tree applications. It is designed to be used in applications where the clock source may be far away, or the clock signal may be corrupted due to noise or EMI. It can also be used to generate clock frequencies with less jitter than traditional clock-generating devices.

The device is available in a small QFN package and is compatible with most common logic families like LVCMOS, LVTTL, and LVPECL. It can also be used as an output buffer for FPGA signals. Additionally, it can be used as an oscillator for timing or data recovery applications.

The THS788PFDT is a programmed-phase-lock loop (PLL) device, where the input clock signal is divided by the selectable N-divider ratio and the output of the PLL is the clock multiplied by the M-divider ratio and with fractional multiplying. The fractional multiplication enables the THS788PFDT to generate any frequency close to the external reference clock. The M-divider ratio can be programmed, allowing the clock frequency to be adjusted without external components.

The device includes an internal charge pump, which eliminates the need for external components. The charge pump is used to generate thevoltage on the VCO to generate the desired frequency. The charge pump is programmed with a selectable current value, which can be optimized for a specific application.

The device includes a differential PECL driver that has the capability of driving 400mV into a 28uA output. This differential output buffer allows for improved signal integrity and noise margins at high data rates. The differential output can be used to drive data and clock signals into high-speed SERDES channels.

The THS788PFDT also includes an adjustable output skew setting. This allows the device to move the positive and negative output edges to compensate for trace delays on the board. This is useful in applications where the device may be located far away from the data source and the clock must be phase-aligned before reaching the destination.

The THS788PFDT device can be used in a variety of applications, including clock tree applications, where it can be used to eliminate clock jitter and reduce power consumption. It can also be used in timing or data recovery applications, to generate any frequency close to the reference clock.

The device is also very suitable for driving high-speed SERDES channels in applications requiring data transfer. With the adjustable output skew setting and the differential output buffer, it can be used to ensure high signal integrity in high-speed gaming or networking applications. Finally, it can also be used as an oscillator for generating low jitter clock signals.