TMS320VC5509AZAYR

Due to market price fluctuations, if you need to purchase or consult the price. You can contact us or emial to us:   sales@allicdata.com

Description

The TMS320VC5509A fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

Features

   1. High-Performance, Low-Power, Fixed-Point TMS320C55 Digital Signal Processor

       − 9.26-, 6.95-, 5-ns Instruction Cycle Time

       − 108-, 144-, 200-MHz Clock Rate

       − One/Two Instruction(s) Executed per Cycle

       − Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]

       − Two Arithmetic/Logic Units (ALUs)

       − Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses

   2. 128K x 16-Bit On-Chip RAM, Composed of:

       − 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit

       − 192K Bytes of Single-Access RAM (SARAM) 24 Blocks of 4K × 16-Bit

   3. 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)

   4. 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)

   5. 16-Bit External Parallel Bus Memory Supporting Either:

       − External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:

           1. Asynchronous Static RAM (SRAM)

           2. Asynchronous EPROM

           3. Synchronous DRAM (SDRAM)

       − 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities

   6. Programmable Low-Power Control of Six Device Functional Domains

   7. On-Chip Scan-Based Emulation Logic

   8. On-Chip Peripherals

       − Two 20-Bit Timers

       − Watchdog Timer

       − Six-Channel Direct Memory Access (DMA) Controller

       − Three Serial Ports Supporting a Combination of:

            1. Up to 3 Multichannel Buffered Serial Ports (McBSPs)

            2. Up to 2 MultiMedia/Secure Digital Card Interfaces

       − Programmable Phase-Locked Loop Clock Generator

       − Seven (LQFP) or Eight (BGA) GeneralPurpose I/O (GPIO) Pins and a GeneralPurpose Output Pin (XF)

       − USB Full-Speed (12 Mbps) Slave Port Supporting Bulk, Interrupt and Isochronous Transfers

       − Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface

       − Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply

       − 4-Channel (BGA) or 2-Channel (LQFP) 10-Bit Successive Approximation A/D

   9. IEEE Std 1149.1† (JTAG) Boundary Scan Logic

 10. Packages:

       − 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)

       − 179-Terminal MicroStar BGA (Ball Grid Array) (GHH Suffix)

       − 179-Terminal Lead-Free MicroStar BGA (Ball Grid Array) (ZHH Suffix)

 11. 1.2-V Core (108 MHz), 2.7-V – 3.6-V I/Os

 12. 1.35-V Core (144 MHz), 2.7-V – 3.6-V I/Os

 13. 1.6-V Core (200 MHz), 2.7-V – 3.6-V I/Os

Application scenarios

   1. Speech processing:

       - Echo cancellation/speech coding (G.729, etc.)

       - Hearing aid algorithm implementation

   2. Industrial control:

       - Motor servo control (FOC algorithm)

       - Vibration analysis system

   3. Portable device:

       - Digital voice recorder

       - Biosignal acquisition

Peripheral interface

Development support

   1. Tool chain:

       - Code Composer Studio™ (CCS)

       - C/C++ compiler (supports C55x instruction set)

   2. Simulation debugging:

       - JTAG boundary scan (IEEE 1149.1)

       - Real-time data monitoring function

   3. Algorithm library:

       - DSPLIB (optimized math function library)

       - IMGLIB (image processing library)

Hardware design points

   1. Power management:

       - TPS73xx series PMIC is required

       - Strict power-on timing requirements (core before I/O)

   2. Clock system:

       - Support external crystal oscillator (10-50MHz)

       - Built-in PLL (1-15 times frequency)

   3. PCB design:

       - BGA package needs to adopt 6-layer board design

       - Key signal line length matching ±50ps