TPIC6B273DWRG4 Integrated Circuits (ICs)

Logic - Latches

The TPIC6B273DWRG4 is a high-performance logic-level translator that offers low-power, low-voltage, low-skew, dual-supply bus-hold circuitry requiring no pullup or pulldown resistors. This device utilizes two PMOS pass transistors as an active latch, allowing automatic adjusting of the supply-voltage thresholds and hysteresis characteristics. It is designed to interface between two 1.8V to 3.6V buses. The current version of the latch is the TPIC6B273DWRG4, a quad latch that operates over a temperature range of 0°C to +85°C.

Application Field

The TPIC6B273DWRG4 latch is ideally suited for applications requiring low power supply-voltage types, low logic levels, and low skew. Applications include data bus buffers, memory buffers, and level shifters. It is also suitable for ultra-low power designs, as it dissipates only 5 mW of power during the active mode, making it ideal for mobile computing designs.

The TPIC6B273DWRG4 combines two useful features: 1) low-power stand-by mode, allowing the power consumption to be reduced to 0.3 mW, making it well-suited for battery-powered applications; and 2) data-retention mode where the state of the output can be preserved in order to further reduce power consumption during periods of inactivity. This device also comes with a variety of protection features such as reverse-bias output protection, and over-temperature protection.

Working Principle

The TPIC6B273DWRG4 used two PMOS pass transistors as an active latch that allow the supply-voltage thresholds and hysteresis characteristics to be automatically adjusted. When the latch is not active, the pass transistors are not conducting, and the latches are held in a low power stand-by mode. When the latch is activated, the output level will be determined by the input levels. The output level is always lower than the logic high voltage which is 2.7V.

The latch is designed to interface between two 1.8V to 3.6V buses. When the input switches from a low to a high level, the latch is enabled, allowing the voltage that is applied on the buses to be translated to the appropriate level. As the input switches from high to low level, the latch is disabled, and the last state of the output will be held until a new input cycle is encountered.

The output logic level is based on the input voltage level and the reference voltage VbH which is 2.7V. If the input is greater than VbH, the output will be high and if it is less than VbH, the output will be low. The latch has an active low-power standby mode and a low power data retention mode, which helps to reduce power consumption during periods when the latch is not in use. This can help extend the life of batteries.

Conclusion

The TPIC6B273DWRG4 is a quad latch designed to operate over a temperature range of 0°C to +85°C and offers low-power, low-voltage, low-skew and dual-supply bus-hold circuitry. This device is ideally suited for applications requiring the translation of voltages between two buses and is also suitable for mobile computing designs that require ultra-low power stand-by and data-retention modes. The output logic of the latch is determined by the input voltage level and the reference voltage VbH.