XC6SLX9-2FTG256C

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1. Describe

The Spartan®-6 series provides this total system integration function for large applications at the lowest cost. The 13-person series provides an expansion from 3840 logic units to 147443 logic units, saving Based on the mature 45nm low-consumption copper process technology, The Spartan-6 series provides the best balance of cost, consumption and performance, providing a new and more efficient dual-interface 6-input look-up table LUT logic and deep built-in system-level module options. Including 18 Kb (2 x 9) Kb) RAM block, second generation DSP4481, Slice4ADRAM, enhanced mixed-mode module management module, SelectIO™ power optimization technology, high-speed light emitting transceiver, PCI Express® module module, advanced system-level power management module Through AES and Device DNA protection detection mode, configuration options and enhanced IP. These features provide an automatic smart alternative to custom ASIC products with safe and easy-to-use. Spartan-6 FPGA provides the best solution Large-capacity logic design, deep consumer DSP design and cost-sensitive embedded applications. Spartan-6 FPGA is The silicon foundation of the target design platform provides integrated software and hardware components to achieve Designers focus on innovation at the beginning of the life cycle development.

2. Features

    1. Spartan 6 family

        -Spartan-6 LX FPGA: logic optimization

        -Spartan-6 LXT FPGA: High-speed electrolytic connection

    2. Drawing Design

        -Multiple efficient integrated blocks

        -Optimize the selection of I/O standards

        -Alternating pad

        -Large-capacity plastic wire bonding package

    3. Low luminescence and dynamic power consumption

        -45nm process optimized for cost and low power consumption

        -Sleep power-off mode to achieve zero consumption

        -Suspend mode through multiple wake-ups, control enhancements to maintain state and configuration

        -Low power consumption 1.0V core voltage (only LX FPGA, -1L)

        -High-performance 1.2V core voltage (LX and LXT FPGA, -2, -3 and -3N speed grades)

    4. Multi-voltage, multi-standard SelectIO™ interface group

        -Data transfer I/O data transfer rate up to 1,080 Mb/s

        -The best output drivers, each up to 24 mA

        -3.3V to 1.2V I/O standards and protocols

        -Record HSTL and SSTL memory interfaces

        -Hot plug compliance

        -Adjustable I/O conversion rate to increase signal bandwidth

    5. High-speed GTP spark transceiver in LXT FPGA

        -Up to 3.2 Gb/s

        -High-speed interfaces include: Spark ATA, 1G interface A, PCI Express, OBSAI, CPRI, GPON, DisplayPort and XAUI

    6. Integrated module (LXT) for PCI Express design

    7. Bundled with PCI® technical support, unique 33 MHz, 32-bit and 64-bit specifications.

    8. Efficient DSP48A1 three times

        -Arithmetic and signal processing

        -Fast 18 x 18 multiplier and 48-bit accumulator

        -New Zealand and cascading capabilities

        -Pre-adder for auxiliary filter application

    9. Integrated memory controller module

        -DDR, DDR2, DDR3 and LPDDR support

        -Data rate up to 800 Mb/s (12.Gb/s max 8)

        -Multi-port bus structure with independent FIFO to reduce design problems

  10. The logic logic is serious, and the logic capacity increases

       -Optional memory or memory support

       -Efficient 6-input LUT improves performance and reduces consumption

       -Accompanied by bidirectional LUT, suitable for pipeline-centric applications

  11. Block RAM with a wide range of granularity

       -Fast block RAM with byte write enable

       -18 Kb blocks, which can be regularly programmed as two independent 9 Kb blocks of RAM

  12. Surface-enhanced control tiles (CMT)

       -Low noise, mobile alarm clock

       -Digital Clock Manager (DCM) can delete clock error and duty cycle correction

       -Phase-locked loop (PLL) for low-speed clock

       -Simultaneous frequency synthesis of multiplication, division and phase shift

       -16 sluggish induction networks

  13. Simplify configuration and support flow standards

        -2-pin automatic detection configuration

        -Extensive support for SPI (up to x4) and NOR support

        -Powerful Xilinx platform with JTAG

        -MultiBoot supports multi-bit stream remote upgrade, using watchdog protection

  14. Enhance the safety of design protection

        -The only Device DNA tag for design certification

        -AES bitstream washing of large equipment

  15. Use enhanced haptic MicroBlaze™ for fast embedded processing processor

  16. Industry-renowned IP and reference designs feature

3. Configuration

Spartan-6 FPGA stores custom configuration data in SRAM type internal latches. Configure the number of bits Between 3 Mb and 33 Mb, depending on device size and user design implementation options. Configuration storage It is volatile and must be reloaded when the FPGA is powered on. This storage can also be reloaded at any time by pulling The PROGRAM_B pin is low. There are a variety of methods and data formats for loading configurations. The bit-serial configuration can be the master serial mode, where the FPGA generates the configuration clock (CCLK) signal, Or from the serial mode, where the external configuration data source also provides the clock for the FPGA. For byte-wide configurations, The master SelectMAP mode generates the CCLK signal, while the slave SelectMAP mode receives 8 and 16-bit wide transmission. In the main serial mode, the beginning of the bit stream can choose to switch the clock source to The external clock can be faster or more accurate than the internal clock. Available JTAG pins use boundary scan The protocol for loading bit serial configuration data. The bitstream configuration information is generated by the ISE® software using a program called BitGen. Configuration The process usually executes the following sequence:

1. Detect power-on (power-on reset) or PROGRAM_B at low level.

2. Clear the entire configuration memory.

3. The sampling mode pin determines the configuration mode: master or slave, bit serial or parallel.

4. Load the configuration data from the bus width detection mode, followed by the synchronization word, check It is used for the correct device code and ends with a cyclic redundancy check (CRC) of the complete bitstream.

5. Start a user-defined sequence of events: release the internal reset (or preset) of the trigger, choose to wait The DCM and/or PLL lock, activate the output driver, and switch the DONE pin to a high level.

Master Serial Peripheral Interface (SPI) and Master Byte-wide Peripheral Interface (BPI) are two commonly used methods Used to configure the FPGA. The Spartan-6 FPGA configures itself via a direct- connected industry standard SPI serial Flash PROM. When Spartan-6 FPGA is connected to industry standard parallel NOR flash memory, it can configure itself through BPI. Please note that XC6SLX4, XC6SLX25 and XC6SLX25T do not support BPI configuration, use Spartan-6 FPGA in TQG144 and CPG196 packages. Spartan-6 FPGA supports MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored in one Single configuration source. The FPGA application controls which configuration is loaded next and when it is loaded. The Spartan-6 FPGA also includes a unique, factory-programmed Device DNA identifier, which can be used for tracking purposes, anti-clone design, or IP protection. In the largest devices, the bitstream can be copy protected using AES encryption.

4. Function summary

5. I/O electrical characteristics

Single-ended output uses traditional CMOS push/pull output structure to drive high level to VCCO or low level Ground, you can enter the high impedance state. System designers can use many I/O functions to choose between I/O in the design, such as weak internal pull-up and pull-down resistors, strong internal separation termination input resistance, Adjustable output drive strength and slew rate, and differential termination resistance.