FPGA overall structure
The FPGA architecture mainly includes four parts: a Configurable Logic Block (CLB), an Input Output Block (IOB), an Interconnect, and other embedded units.
CLB is the basic logic unit of an FPGA. The actual number and characteristics will vary from device to device, but each CLB contains a configurable switch matrix consisting of 4 or 6 inputs, several selection circuits (multiplexers, etc.) and flip-flops. The switch matrix is highly flexible and is configured to handle combined logic, shift registers or RAM.
FPGAs support a wide range of I/O standards, providing an ideal interface bridge for system design. The I/O in the FPGA is grouped by bank, and each bank can independently support different I/O standards. Today's state-of-the-art FPGAs offer more than a dozen I/O banks that provide flexible I/O support.
The CLB provides logic performance, and flexible interconnect routing is responsible for passing signals between the CLB and the I/O. There are several types of routing, from global low-skew routing designed to implement CLB interconnects (short-line resources) to high-speed horizontal and vertical long lines (long-line resources) within the device, to clocks and other global signals (global-specific Wiring resources). In general, the design software of each manufacturer hides the interconnect routing tasks, which are invisible to the user, thus greatly reducing the design complexity.
Embedded hard core units include RAM, DSP, DCM (Digital Clock Management Module) and other specific interface hard cores.
In general, the larger the device model number, the larger the logical resources that the device can provide. In the FPGA device selection, users need to compare this table according to the business logic resources (CLB), internal blockRAM, interface (high-speed Serdes logarithm), digital signal processing (DSP hard core) and future expansion. Consider the most appropriate logic device for the project.
FPGAs have certain technical difficulties in the practical application of the data center server market, including the following aspects:
1. Higher programming threshold: The hardware description language is different from the software development language, which requires developers to have a deeper understanding of the underlying hardware; therefore, talent has become an important factor limiting FPGA applications.
2. Integration is difficult: FPGA development and application require software and hardware coordination, including system modeling using high-level language, hardware code (circuit) design, hardware code simulation, joint debugging of underlying driver software and hardware logic, and so on.
3. The development cycle is relatively long compared to software: hardware development is more complicated than software development, and the debugging cycle is also lengthened.
4. It is difficult to obtain an independent logical IP.