How to share applications about controlling power-up and shutdown timing

Microprocessors, FPGAs, DSPs, analog-to-digital converters (ADCs), and system-on-a-chip (SoC) devices typically require multiple voltage rails to operate. To prevent lockouts, bus contention issues, and high inrush currents, designers need to turn these power rails on and off in a specific order. This process is called power sequencing or power sequencing, and there are many solutions that can be used to achieve sequencing.

In addition, various power sequencers, monitors, and monitors that are designed to effectively boost and shut down also employ voltage and current level monitoring techniques to calculate power levels in order to protect complex integrated circuits and subassemblies. .

This article details power sequencing, discusses power sequencing specifications and techniques, and how to use a power sequencer to achieve specified power rail timing and sequencing.

Why pay attention to power sequencing?

FPGAs and similar complex integrated circuits (ICs) can be internally broken down into multiple power domains. Most of these ICs require a specific sequence when starting or shutting down the device. For example, FPGAs typically require powering up the core logic, I/O, and auxiliary circuits, respectively.

Its core usually includes the processor and basic logic unit of the FPGA. This power domain features low voltage, high current power specifications. Due to the extremely low voltage, it is extremely accurate, and due to the dynamic nature of the digital load, the transient performance must be excellent. I/O represents the various inputs and outputs of the FPGA. The voltage requirements depend on the type of interface. In general, the voltage level needs to be greater than the voltage level of the core. The current requirements depend on the type, number and speed of the I/O.

Auxiliary circuits include noise-sensitive analog circuits in FPGAs such as phase-locked loops (PLLs) and other analog circuit components. Although the current requirements are quite low, the ripple voltage is a big problem and the ripple voltage must be minimized. Ripple in the analog section can cause excessive jitter and phase noise in the PLL and can cause spurious responses to the amplifier.

Powering the power supplies in each power domain in the wrong order can cause problems and can cause damage to the FPGA. It is important to consider that the I/O section is based on the tri-state bus to send and receive data, while the core is responsible for handling I/O control. If the I/O power domain is powered up before the core, the I/O pins will end in an indeterminate state. If the external bus components are powered up, there may be bus contention issues that cause high currents in the I/O drivers. Therefore, the kernel should be started before the I/O power domain. Be sure to check the vendor's FPGA specifications for recommended power-up and shutdown sequences and the maximum differential voltage between the rails.

Similarly, devices such as power op amps have two power domains: the analog domain and the digital domain. The digital domain provides power to the amplifier's diagnostic status flags to identify overheating and overcurrent conditions. In addition, the digital domain also supports the amplifier's enable/disable function. The device specification requires that the digital domain be powered up prior to the analog power supply so that these status flags will function properly before the analog domain powers up. The purpose of this is to prevent possible damage to the device.

Power sequencing method

There are usually three types of multitrack sequencing (Figure 1). The most common method is sequential sequencing, which is to first turn on a power rail, then delay, and then turn on the next power rail. The purpose of setting the delay is to ensure that the first rail is regulated before the second rail is started.

Figure 1: Three power sequencing techniques.

Regardless of the technology used, the voltage must rise in a monotonous manner. Otherwise, the device may not initialize properly due to an unexpected voltage drop during startup. (Photo: Digi-Key Electronics)

The second sequencing technique is ratio sequencing. In this technique, the power rails are simultaneously activated and simultaneously reach their respective rated voltages. This requires the power rail rise time to be proportional to the power rail voltage to achieve regulation at the same time.

Some devices may not be able to withstand the instantaneous voltage difference that occurs before regulation is reached. This can cause the device to consume higher current on a single supply during this time.

The third method is simultaneous startup, which minimizes transient voltage differences and reduces the size and period of these pressures. A common way to implement this method is to power up at the same time, that is, the voltage rails rise together at the same rate, and the higher voltage rails (usually the I/O voltage rails) reach their final in the lower voltage rail or the core voltage rail. After the value continues to rise.

Regardless of the technology used, the voltage must rise in a monotonous manner. Otherwise, the device may not initialize properly due to an unexpected voltage drop during startup.

In addition, a soft start can be used to limit the inrush current during startup. This practice limits the current during startup, allowing the rail rail capacitance to be gradually charged at startup.

The power-off sequence is usually specified to be the reverse of the startup sequence.

The choice of which startup or shutdown technique to use should depend on the specifications of the device.

Power sequencing example

Simultaneous startup is relatively easy to set up. You need to connect the highest voltage output to the input of the lower voltage regulator (Figure 2).

Figure 2: Simultaneous startup of a 5 V supply and a 3.3 V supply can be achieved by daisy-chaining the regulator.

In this example, the higher voltage is a 5 V supply. This 5 V voltage is also fed into the 3.3 V regulator. The figure shows the voltage output when the 5 V and 3.3 V supplies rise simultaneously and the minimum dropout voltage reaches the 3.3 V supply regulation point.

This sequencing technique is preferably implemented using a sequencer integrated circuit such as the Texas Instruments LM3880. The LM3880 is a simple power sequencer that can be used to control multiple independent regulators or power supplies through the regulator or power supply enable input.

When the LM3880 starts up, the three output flags are released in sequence after each delay time, allowing the connected power supply to start. During shutdown, the output flags will follow the reverse order. The following image is a design example using the LM3880, designed using Texas Instruments' WEBENCH Power Designer software (Figure 3). This free software tool not only helps engineers design power-related circuits, but also provides schematics, bills of materials, and simulation results. The figure shows the schematic, chart, enable, and three flag outputs.

The delay time and order of the LM3880 are fixed, but can be customized at the factory via the built-in EPROM. In addition, Texas Instruments provides capacitor programmable delay for the LM3881 sequencer.

Figure 3: Screenshot of the WEBENCH Power Designer software from Texas Instruments shows a schematic of the LM3880 design and an enable input and output flag diagram for controlling an external voltage regulator or power supply.

Analog Devices' LTC2937 sequencer/voltage monitor is a slightly more complex power control device. Like the LM3880, the LTC2937 can control the timing and time delay of up to six power supplies or regulators (Figure 4).

Figure 4: The LTC2937 can control up to six power supply timings while also monitoring the supply rail voltage. Multiple devices can be synchronized by a single wire, and up to 300 power supplies can be controlled.

In addition to sequencing up to six power rails, this sequencer monitors the voltage on these rails for overvoltage, undervoltage, voltage drop, and runaway power-on detection. In the event of a fault, you can program the device to shut down or restart the power supply. Error conditions will be logged to the internal EEPROM. The LTC2937 can be programmed and controlled via I2C or SMBus. Programming is done with Analog Devices' LTpowerPlay GUI software. The EEPROM is self-contained and requires no software. If your system requires more than six power rails, you can control up to 300 power supplies by simply linking multiple LTC2937s together.

For complex multi-core processors, FPGAs, and other SOC devices, Texas Instruments offers the TPS650860 configurable multi-rail power management unit. This single IC, 5.6 V - 21 V input management unit contains three buck controllers, three buck converters, one sink or pull low dropout (LDO) linear regulator, and three Low voltage input LDO, voltage regulator and three load switches (Figure 5).

Figure 5: The Texas Instruments TPS650860 functional block diagram shows 13 fully time-controlled regulated outputs.

The device has 13 regulated outputs to meet the needs of FPGAs or other load devices.

Its buck converter has a built-in power stage, while the buck controller requires an external power stage. Both the converter and the controller integrate a voltage-sensing input to monitor the power output for sequencing control. Its load switch has slew rate control that can be programmed for any of the three sequencing types (sequence, ratio, or simultaneous).

The TPS650860 is controlled via the I2C interface, allowing simple control via an embedded controller or associated SoC manager. This power management IC has leading control flexibility.

If you want to know more, our website has product specifications for the controlling power-up and shutdown timing, you can go to ALLICDATA ELECTRONICS LIMITED to get more information