What opportunities does RISC-V bring to FPGA?
The development speed of RISC-V is much faster than I expected. I think this will bring a huge opportunity to FPGA, so that it can eat ASIC and ASSP more. Most SoCs use FPGAs on their way to ASICs, and first use FPGA-based simulation or prototype design for verification. At the same time as ASIC development, many SoC projects began to be released in the form of FPGAs. And RISC-V can help FPGA delay or even cancel the plan of developing ASIC.
The good news for FPGA companies is that the work of the ecosystem is increasingly being done by the RISC-V open source community. The heavy responsibility of developing ISA, tool chain, and software stack no longer falls on one company. The only step left to insert FPGAs into the RISC-V ecosystem is to productize the RISC-V core for FPGAs and migrate to ASICs.
RISC-V will change the pattern of embedded processors
Next-generation SoCs will rely heavily on customized processors to implement domain-specific architectures (DSA) to achieve performance and power consumption improvements that Moore's Law can no longer provide. First-tier companies like Apple, Qualcomm and Samsung have been doing this for many years. They have large design teams and expensive architecture licenses that can customize ARM processors. Other companies have launched their own hardware accelerators or added custom instructions to cheap processor cores like ARC and Tensilica.
For many edge-based devices, ARM customization is not an affordable mainstream choice. Both ARC and Tensilica are proprietary ISAs. With the emergence of RISC-V, they will not be able to expand to the industry's common processor platform.
RISC-V has become the first choice of innovators. It has the characteristics of low power consumption-from the beginning there is a clean starting point, it can be implemented with the minimum instruction set, avoiding the bloat of the traditional ISA. Its development takes into account architectural innovation-support for 16-bit to 128-bit instructions, custom extensions, multi-core, multi-core, multi-core and hardware acceleration-it has become the number one ISA for the development of hardware-based network security systems.
ARM's market dominance will be guaranteed by traditional software and its monopoly in the mobile field in the next few years. However, the open source RISC-V innovation wave will change other areas of embedded processors as we know them:
Large-scale collaboration will build the RISC-V ecosystem so that proprietary ISA will be eliminated. MIPS, ARC, Tensilica, MicroBlaze, and Nios will all fade out. The main innovation tools will be RISC-V and FPGA. The wave of innovation will flow to having the best RISC- V-supported FPGA company RISC-V has the conditions required to become an ASIC processor platform. The RISC-V open source community has completed the increasingly powerful RISC-V ecosystem. It is worth repeating that the important task of developing ISA, tool chain and software stack is no longer borne by one company. The only thing required to insert an FPGA into the RISC-V ecosystem is a RISC-V core produced for the FPGA and portable to ASICs.
I said earlier that RISC-V can help FPGA incentives delay or even cancel the plan to develop ASICs. Ironically, increasing the development path from FPGA to ASIC is an opportunity to increase FPGA revenue. Let us look at a simple example.
As FPGA integrates more and more standard components, such as the hard cores of standard components such as Ethernet, USB, PCIE, DDR, and multi-core processor subsystems, the opportunity to transform to ASIC has increased exponentially. The new application workload requires architecture and memory optimization to exceed the frequency of the new application workload, making SoC performance less sensitive to the low speed of programmable logic. Surprisingly, the new calculation results show that even MCUs (microcontrollers) (standard off-the-shelf ASIC SoCs) have opened the door to FPGAs running soft cores of processors.
At high-end MCUs (32/64-bit processors, GHz frequency), new workloads that require DSA will eliminate general-purpose MCUs as an option. The next option is Configurable SoC (cSoC)-MCU with FPGA programmable logic. If DSA is mapped to cSoC and meets performance, power consumption and cost constraints, then SoC will switch from MCU to cSoC.
If not, then the next option is spin ASIC, which will start with FPGA prototype or simulation, because the only sure way to verify the performance of the architecture is to run the application code on the hardware. In this process, an unexpected solution may be a general-purpose FPGA whose soft processor core can provide sufficient performance. If the general-purpose FPGA meets the power consumption and cost requirements of the product, it will switch from an MCU to a general-purpose FPGA with a soft-core processor.
You can see how these numbers are calculated from the table below, where a general-purpose FPGA with a processor soft core uses a lower cost and complexity solution to provide good enough performance (the scenario illustrates an application, The MCU must be replaced by a DSA with a hardware accelerator that can offload 90% of the work from the general-purpose processor and execute it at 10 times the speed).
At the low end (16-bit processor, "100MHz), the market is promoting the integration of MCU, FPGA and other board chips to improve performance, power consumption and cost. FPGA vendors responded with cSoC ten years ago. Although many MCUs have achieved transformation, many other MCUs have not achieved transformation due to cost or system incompatibility. These remaining MCU applications will lose market share due to the new degrees of freedom provided by cheap FPGAs and RISC-V soft cores.
In the near future, FPGAs with RISC-V cores will become the next generation of innovative platforms based on IoT edge devices, which is inevitable. These designs will start with FPGA-based prototype verification and simulation. In this process, many systems will find that FPGA-based RISC-V solutions can provide sufficiently good performance, power and cost. I think it is only a matter of time before all FPGA vendors provide RSIC-V soft core products. This will benefit both system customers and FPGA vendors themselves.
While we are talking about changes, we are also likely to see that RISC-V-based innovations will also use cloud computing extensively. Compared with traditional simulators, FPGA-based simulators can save a lot of cost, but not everyone can take advantage of this advantage because it is very complicated. Having a simplified IoT device simulation capability in the cloud--just like how AWS-FPGA simplifies data center acceleration--can truly change the rules of the game.
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