What is the use of FPGA with on-chip high-speed network?
Simplify high-speed data distribution in the entire FPGA logic array
In various traditional FPGA architectures, bidirectional read/write operations on off-chip memory connected to FPGA and external high-speed data sources connected to it require data to go through a long and segmented route in the FPGA logic architecture path. This restriction not only limits the bandwidth, but also consumes the wiring resources required by the user design in the logic array, which brings challenges to FPGA designers in terms of timing closure, especially when other logic functions increase device utilization. time.
Using Speedster7t's NoC to transfer data from external sources to FPGA and memory is much easier than using traditional FPGA architecture to complete the same work. Speedster7t NoC enhances the traditional programmable interconnection in the FPGA array. The NoC is like a highway network superimposed on a city street system. Although the traditional, programmable interconnect matrix in Speedster7t FPGAs is still suitable for slower local data traffic, NoC can handle more challenging, high-speed data streams.
Each row or column in the NoC is implemented as two 256-bit unidirectional data channels running at a fixed clock rate of 2 Ghz. The rows have east/west channels, and the columns have north/south channels, allowing each NoC row or column to simultaneously handle 512 Gbps of data traffic in each direction. All in all, these channels can transmit large amounts of data in the FPGA array by writing simple Verilog or VHDL codes. These codes support the communication between FPGA and NAP and connect to the NoC highway network.
The figure below shows the data transfer between various points in NoC. The logic of point 1 and point 2 respectively instantiate a horizontal NAP. NAP can send and receive data, but each individual data stream only faces one direction. Similarly, the logic of point 3 and point 4 instantiates a vertical NAP and can send data streams between each other.
Automatically connect PCIe interface to storage
In the current FPGA, designers must consider the delays in the device due to the connection logic, wiring, and the location of input and output signals when connecting a high-speed interface to a storage device connected to the FPGA for reading and writing. In order to implement basic interface functions, it usually takes a lot of time to construct a simple storage interface during the design process.
In the Speedster7t architecture, the task of connecting the embedded PCIe Gen5 interface to the connected GDDR6 or DDR4 memory can be automatically handled by the peripheral NoC, and the designer does not need to write any RTL to establish these connections. Because NoC is connected to all peripheral IP interfaces, designers have great flexibility when connecting PCIe to any memory interface of GDDR6 or DDR4. In the example below, NoC can provide enough bandwidth to continuously support PCIe Gen 5 communication streams connected to any two channels of GDDR6 memory. This kind of high bandwidth connection can be realized without consuming any FPGA logic array resources, and the design time is almost zero. Users only need to enable PCIe and GDDR6 interfaces to send transactions on NoC.
If you want to know more, our website has product specifications for FPGA, you can go to ALLICDATA ELECTRONICS LIMITED to get more information