Electrical parameters and CMOS circuit of TTL circuit
Electrical parameters and CMOS circuit of TTL circuit
TTL circuit
1) the input terminal usually has a clamping diode, which reduces the effect of reflection interference.
2) low output resistance, capacitance load increase capacity.
3) there is a large margin of noise.
4) use +5V power supply.
In order to perform normal function, the device should be operated under recommended conditions.
The working conditions for 74LS series circuits are:
1) the supply voltage should be in the range of 4.75 ~ 5.25V.
2) the ambient temperature is 0 to 709C.
3) high level input voltage VH > 2V, low level input voltage VSL<0.8V.
4) the output high level current should be less than 400 A, and the output low level current is less than 8 ma.
5) The operation frequency is not high, the typical low-level to high-level transmission delay time is 15 ns, the high-level transmission delay time is 12 ns, the maximum operating frequency is 33 MHz.
cmos circuits
1) Power supply voltage should be strictly maintained in the range of 5V 0.5V, too high damage equipment, too low normal operation. In test, DC power supply with good stability and small internal resistance is usually used. When using, special attention should be paid to both the power supply and the ground. Otherwise, the equipment will be damaged due to excessive current.
2) It is better not to suspend the excess input when suspended, which may not affect the logic function of the gate (and non-gate), but is susceptible to interference when suspended, for this reason, with the door, and non-door redundant input, can be directly connected to V, or through a common resistance (thousands of ohms) to VE. If the front drive is strong, the redundant input can be connected to the user terminal; at least one gate circuit needs to be directly grounded, and there is an extended end, and the power supply is not allowed to be directly connected to the end. If the resistance is grounded through resistance, the magnitude of the resistance directly affects the state of the circuit.
3) The output terminal is not allowed to be directly connected to the power supply or the ground, and the output of different output signals is not allowed to be directly connected (except the collector open gate and the three-state gate).
4) the load capacity of the circuit, that is, the fan out coefficient, should be considered so as not to affect the normal operation of the circuit.
5) when working at high frequencies, the peak current interference should be suppressed by shortening the wire and shielding interference sources.
6) When the external input signal edge changes very slowly (rising edge or falling edge is less than 50-100 ns/V), the shaping circuit must be added to improve it.