71V3558SA133BQG

Write Cycle Time - Word, Page:	--
Base Part Number:	IDT71V3558
Supplier Device Package:	165-CABGA (13x15)
Package / Case:	165-TBGA
Mounting Type:	Surface Mount
Operating Temperature:	0°C ~ 70°C (TA)
Voltage - Supply:	3.135 V ~ 3.465 V
Memory Interface:	Parallel
Access Time:	4.2ns
Series:	--
Clock Frequency:	133MHz
Memory Size:	4.5Mb (256K x 18)
Technology:	SRAM - Synchronous ZBT
Memory Format:	SRAM
Memory Type:	Volatile
Part Status:	Active
Packaging:	Tray

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Memory71V3558SA133BQG is a single-chip high-speed synchronous DRAM (dynamic random access memory), mainly used to expand the buffer memory of high-end computer networking equipment and other storage space to meet the needs of large-capacity storage.71V3558SA133BQG is mainly composed of an array of memory cells, a refresh control circuit, a write/read control circuit, an address register and an I/O buffer register. The number of memory cells is 64M, the page size is 256, the refresh need mode is Full Array Refresh (FAR), and the cycle time is 8K. The built-in state machine defines the access flow of information of the device, and a I2C compatible Bus Interface unit is provided to accept the instruction from the host controller, so as to realize the necessary address and command generation, serial data input and output and timing control, etc. 71V3558SA133BQG features high speed operation, low power consumption, simple operation and wide application. The single chip uses an advanced, highly reliable triple-level coded architecture to realize page access and low-power burst cycle to reduce standby current. It also has an auto-precharge and power-down mode, which can save power and improve data reliability. In addition, a DQM (Data Mask) pin is provided for parity check or ECC (Error Correcting Code) operation. 71V3558SA133BQG is widely used in the fields of computer networking equipment, industrial control equipment, 3G / 4G wireless communication base station, ATM and FPD (Flat Panel Display) etc. It is suitable for occasions with high requirements for system performance, such as heavy loading servers, high-end routers, high-end network switches, network cameras, optical communication equipment and so on.71V3558SA133BQG has become an important part of modern computer systems, and its working principle has become more and more complicated. The basic working principle is that, the device supplies an externally applied voltage VDD to the CMOS transistor in turn and then the stored data is output. Specifically, when a read instruction is received in the form of a series of command signals, the address selection logic selects a row of memory cells and then sends a row activation (ACT) instruction to rows address latch. After the row is activated, the row address latch generates a corresponding row address and then sends it to the bank selector. The corresponding double clock signal is sent to eight pairs of data in and data out gates, the memory cell voltage supplies the voltage level of VDD to both sides of the data in gate, when the external voltage acts on the DOUT pin, the data in gate is opened, and the potential of the adjacent memory cell is coupled out, thus, the output data is obtained.

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