74HC273D,653

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1. General description

The 74HC273D,653 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and advantages

    1. Wide supply voltage range from 2.0 V to 6.0 V

    2. CMOS low power consumption

    3. High noise immunity

    4. Latch up performance exceeds 100 mA, in line with JESD 78 Class II Level B

    5. Conforms to JEDEC standards:

        - JESD8C (2.7V to 3.6V)

        - JESD7A (2.0 V to 6.0 V)

    8. Input level:

        - For 74HC273: CMOS level

        - For 74HCT273: TTL level

    9. Universal clock and master reset

  10. 8 positive edge trigger D-type flip-flops

  11. ESD protection:

        - HBM JESD22-A114F exceeds 2000 V

        - MM JESD22-A115-A exceeds 200 V

  12. A variety of package options

  13. Specified ranges are -40 °C to +85 °C and -40 °C to +125 °C

3. Pin configuration

4. Pin description

5. Package outline