74HCT138N,652

1. General description

74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) Up to eight mutually exclusive outputs (Y0 to Y7). The device has three enable inputs (E1, E2 and E3). Unless E1 and E2 are low and E3 is high, each output will be high. This multi-enable function allows easy parallel expansion to 1 of 32 bits (5 to 32 lines) The decoder only has four "138" ICs and one inverter. ‘138’ can be used as eight outputs By using one of the valid low-enable inputs as the data input and The remaining enable inputs are used as strobe pulses. The input includes clamping diodes. So you can use The current limiting resistor connects the interface input to a voltage exceeding VCC.

2. Features and benefits

    1. Complies with JEDEC standard no. 7A

    2. Input levels:

        - For 74HC138: CMOS level

        - For 74HCT138: TTL level

    3. Demultiplexing capability

    4. Multiple input enable for easy expansion

    5. Ideal for memory chip select decoding

    6. Active LOW mutually exclusive outputs

    7. ESD protection:

       - HBM JESD22-A114F exceeds 2000 V

       - MM JESD22-A115-A exceeds 200 V

    8. Multiple package options

    9. Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Pinning information

4. Functional diagram

5. Package outline