85310AYI-01LFT

Series:	--
Packaging:	Tape & Reel (TR)
Part Status:	Active
Type:	Fanout Buffer (Distribution), Multiplexer
Number of Circuits:	1
Ratio - Input:Output:	2:10
Differential - Input:Output:	Yes/Yes
Input:	HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output:	ECL, LVPECL
Frequency - Max:	700MHz
Voltage - Supply:	2.375 V ~ 3.8 V
Operating Temperature:	-40°C ~ 85°C
Mounting Type:	Surface Mount
Package / Case:	32-LQFP
Supplier Device Package:	32-TQFP (7x7)
Base Part Number:	ICS85310-01

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85310AYI-01LFT Application Field and Working PrincipleThe 85310AYI-01LFT is a high-performance, low-cost clock buffer from Texas Instruments. It is designed to provide multiple copies of a single clocking signal with minimal skews between the outputs. This clock buffer is suitable for a variety of applications including High Speed Clock Distribution, Clock Network Management, Buffering of external clocks, and synchronization of multiple clocks.The 85310AYI-01LFT is a low jitter CMOS device, with skew-controlled outputs, which can be used in a range of applications. It is capable of providing high frequency clock signals from one input source, with low jitter and high common-mode noise immunity. It features a differential input buffer, both series and parallel output buffers, and multiple skew-controlled output clocks. It also features a programmable phase-locked loop (PLL) that allows it to be used as a clock multiplier, as well as a clock divider. The 85310AYI-01LFT supports a variety of output formats, including LVDS, LVPECL, CML, and SNC.The 85310AYI-01LFT features a built-in phase-locked loop (PLL). This allows it to be used as both a clock launcher and a clock buffer. The PLL generates an output clock from an input reference. The frequency of the output clock can be selected by programming its Control Register. The output clock can be either a multiple or fractional multiple of the input clock. This means that it can also act as a clock divider. The PLL also includes an internal VCO, low-noise charge-pump, loop filter and PLL control logic. These components provide accurate clock rate and phase information and are used for jitter attenuation.The 85310AYI-01LFT also includes an on-chip logic circuit for monitoring the input clock signal. This means that it can detect any misalignment or discontinuity in the clock signal. If an error is detected, the logic circuit will reset the PLL, which ensures that the output clock will remain synchronized with the input clock.The 85310AYI-01LFT clock buffer is suitable for use in a variety of clock synchronization and distribution applications. It can be used to synchronize multiple system clocks and provide Clock-Tree Synthesis, or distribute a single clock source to multiple boards or modules. It can also be used to buffer external clocks, such as the PCIe clock. The 85310AYI-01LFT provides a variety of output frequencies, with low jitter and low propagation delay. This makes it ideal for High Speed Clock Distribution and Clock Network Management applications.

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