85310AYI-21LN

Series:	--
Packaging:	Tray
Part Status:	Obsolete
Type:	Fanout Buffer (Distribution)
Number of Circuits:	2
Ratio - Input:Output:	1:5
Differential - Input:Output:	Yes/Yes
Input:	HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output:	ECL, LVPECL
Frequency - Max:	700MHz
Voltage - Supply:	2.375 V ~ 3.8 V
Operating Temperature:	-40°C ~ 85°C
Mounting Type:	Surface Mount
Package / Case:	32-LQFP
Supplier Device Package:	32-TQFP (7x7)
Base Part Number:	ICS85310-21

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Clock/Timing - Clock Buffers, DriversThe 85310AYI-21LN is a dual passive clock buffer that is part of the multifunctional latching clock buffer product family from Skyworks Solutions. It is the only device with an integrated latching circuit, providing configurable level inversion, non-overlap, perfect-skate, and asymmetric-skate outputs. The device helps reduce system complexity, BOM count, size, and power consumption by providing a flexible solution for ultra-low jitter clock generation and distribution, compared to multiple PLLs and dedicated fanout buffers. The dual passive clock buffers of the 85310AYI-21LN make it ideal for applications such as servers, storage systems, and storage media players, clock and data recover, networking, broadcasting, microwave-based systems, and many more. This product family also provides clock synchronization, frequency and phase management capabilities, while accurately preserving signal integrity. The 85310AYI-21LN is designed to provide an incredibly low jitter source in single ended, dual ended, or separate output configurations. It uses differential input stages that provide superior signal-to-noise ratio and EMI/RFI suppression. The clock buffer is fully programmable for fanout, symmetric and asymmetric latching, clock signal switching, and signal level inversion, making it easy to configure for related applications. The 85310AYI-21LN is composed of four input pairs that connect to a dedicated internal latching circuit with perfect-skate, asymmetric-skate, non-overlap, and data signal level inversion protocols. The internal latching circuit is complemented by a low jitter clock PLL and dynamic skew compensation to reduce overall system jitter. Each input has a programmable level inversion setting, two output enable pins, an async reset pin, and a power management pin. The 85310AYI-21LN is manufactured using an advanced SOI process, and is created with an advanced clock buffer architecture to ensure high reliability, accuracy, and low jitter. The device also meets all applicable thermal and environmental requirements. The family of products is available in various configurations that allow designers to choose the best solution to meet their system requirements. The 85310AYI-21LN clock buffer is a robust, yet cost-effective high-speed device that helps provide low-jitter, low-power solutions for clock distribution and synchronization. By providing multiple high-performance features, this product family can improve the circuit performance across an entire system, including systems that employ high-speed and high-energy clock signals.

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