ADE7878ACPZ-RL

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1. Describe

ADE7854/ADE7858/ADE7868/ADE7878 have high precision, Three-phase energy metering IC with serial interface And three flexible pulse outputs. ADE78xx devices include Second-order Sigma-Delta (Σ-Δ) analog-to-digital converter (ADC), digital integrator, reference circuit and all The total number of executions (basic and Harmonic) active, reactive (ADE7878, ADE7868 and ADE7858), apparent energy measurement and effective value calculation, only fundamental active and reactive energy Measurement (ADE7878) and effective value calculation. Fixed function A digital signal processor (DSP) performs this signal processing. The DSP program is stored in the internal ROM memory. ADE7854/ADE7858/ADE7868/ADE7878 are suitable for Measure various three-phase active, reactive and apparent energy Configuration, such as wye or delta service, with three There are four more lines. ADE78xx devices provide system calibration The characteristics of each phase, namely the root mean square offset correction, the phase Calibration and gain calibration. CF1, CF2 and CF3 logic The output provides a variety of power information options: total active power, The sum of reactive power and apparent power, or the effective value of current Value, and the basic active and reactive power. ADE7854/ADE7858/ADE7868/ADE7878 contain waveform sampling registers that allow access to all ADC outputs. this The device also contains power quality measurements, such as Short time low voltage or high voltage detection, short time Large current changes, line voltage cycle measurement and The angle between phase voltage and current. Two serial interfaces, SPI and I2C. Can be used to communicate with ADE78xx. Some kind Dedicated high-speed interface, high-speed data acquisition (HSDC) port, can be used with I2 C provides Access ADC output and real-time power information. There are also two ADE7854/ADE7858/ADE7868/ADE7878 Interrupt request pins IRQ0 and IRQ1 indicate that it is enabled An interrupt event has occurred. For ADE7868/ADE7878, three Specially designed low-power mode to ensure continuity Energy accumulation when ADE7868/ADE7878 is in a tampered state. ADE78xx is available at 40-pin LFCSP, lead-free package.

2. Feature

Highly accurate; support EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22 and IEC 62053-23 standards, and 3-phase, 3-wire or 4-wire (delta or star) and other three-phase business compatibility The phase and the entire system provide total (fundamental and harmonic) active, reactive, and apparent energy, as well as fundamental active/reactive energy. At TA = 25°C, within the dynamic range of 1000 to 1, the active error is less than 0.1%. When TA=25°C, the error of active and reactive energy in the dynamic range of 3000~1 is less than 0.2%. Support current transformer and di/dt current sensor. When TA=25°C, the dedicated ADC channel for neutral current input has a dynamic range of 1000 to 1, and the root mean square error of voltage and current is less than 0.1%. Provides the sum of the sampled waveform data of all three-phase and neutral currents. Fundamental active, reactive and apparent power are empty. Low load threshold level. The low battery mode monitors the phase current for tamper-proof detection. Used for battery power input current and phase angle measurement in the voltage channel, used for missing neutral operation, with a typical error of 0.3°. Wide power supply voltage operation: 2.4 V to 3.7 V, with external overdrive capability. Single 3.3 V power supply with 40 Lead Frame Chip Scale Package (LFCSP), lead-free operating temperature: −40°C to +85°C Flexible I2C, SPI and HSDC serial interface

3. Application

    Electric energy metering system

4. Pin configuration

5. Digital signal processor

ADE7854/ADE7858/ADE7868/ADE7878 include a fixed Function Digital Signal Processor (DSP) calculates all power And the root mean square value. It contains program memory ROM and data Memory RAM. The program for power and root mean square calculation is Stored in the program memory ROM, the processor executes Every 8 kHz. The calculation ends by Set bit 17 (DREADY) in the STATUS0 register to 1. one The interrupt attached to this flag can be enabled by setting bit 17 (DREADY) is in the MASK0 register. If enabled, the IRQ0 pin is Set to low, the status bit DREADY is set to 1 at the end calculate. The status bit is cleared and the IRQ0 pin is set Set to high level by writing to the STATUS0 register using bit 17 (DREADY) Set to 1. The registers used by the DSP are located in the data memory RAM, the address is between 0x4380 and 0x43BE. width This memory is 28 bits. In the DSP core, the DSP contains a Two-stage pipeline. This means that when a single register needs To initialize, two more writes are required to ensure The value has been written to RAM, if there are two or more registers Need to initialize, the last register must write two more To make sure that the value has been written to RAM. As mentioned in the power-on procedure section, when power-on Or after hardware or software reset, DSP is in idle mode. No instructions are executed. All registers located in the data Memory RAM is initialized to 0, their default value, and they Can read/write without restriction. Run register, Used to start and stop the DSP, cleared to 0x0000. run Register needs to write 0x0001 to start DSP Code execution. Protect the integrity of the data stored in the data storage DSP RAM (address between 0x4380 and 0x43BE), Provide write protection mechanism. by default, The protection is disabled and the registers are placed at 0x4380 and 0x43BE can be written unlimitedly. When protecting Enable, write to these registers is not allowed. Register can Always read, unrestricted, independent of writing Protection status. To enable protection, write 0xAD to the internal 8 bits The register is located at address 0xE7FE, then write 0x80 To the internal 8-bit register at address 0xE7E3. It is recommended to enable write protection The register has been initialized. If any RAM-based data storage The register needs to be changed, just disable the protection, Change the value, and then re-enable the protection. Have There is no need to stop the DSP to change these registers. To disable the protection, write 0xAD to the internal 8 bits The register is located at address 0xE7FE, then write 0x00 To the internal 8-bit register at address 0xE7E3.

6. Line loop reactive energy accumulation mode

As described in Online Cycle Active Energy Accumulation Mode part, in the online cycle energy accumulation mode, Energy accumulation can be synchronized with voltage The channel crosses zero so that reactive energy can be accumulated for an integer number of half-line cycles. In this mode, ADE7858/ADE7868/ADE7878 transmit Reactive energy accumulated in 32-bit internal accumulator After register to xVARHR or xFVARHR register Integer of line period. The number of half-line cycles is specified in the LINECYC register. The line loop reactive energy accumulation mode is set by bit 1 (LVAR) in the LCYCMODE register. The total reaction energy accumulated in an integer number of half-line cycles or zero crossings can be used in the var-hour accumulation register after detecting the number of zero crossings specified in the LINECYC register. When using the line cycle accumulation mode, bit 6 (RSTREAD) of the LCYCMODE register should be set to Logic 0, because reading of the reset var-hour register is not available in this mode.

7. Current Channel ADC

ADC and signal processing path current channel input IA (IB and IC are the same). The ADC output is a signed twos complement 24-bit data word with a measurement speed of 8 kSPS (thousands of samples per second). With specified full-scale analog input signal ±0.5 V, the ADC produces its maximum output code value. Full-scale voltage signal of differential input (IAP and IAN). ADC output at−5,928,256 (0xA58AC0) and +5,928,256 (0x5A7540). this Input IN corresponds to three-phase neutral current System (only for ADE7868 and ADE7878). if not There is a neutral wire, connect this input to AGND.