ATMEGA1284P-MU

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1. Describe

The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features: 16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three (four for ATmega1284/1284P) flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented two-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conve ntional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true ReadWhile-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits

2. Feature

    1. High-performance, low-power 8-bit Atmel® AVR® microcontrollers

    2. Advanced RISC architecture

        - 131 powerful instructions—mostly single-clock cycle execution

        - 32 × 8 general purpose working registers

        - fully static operation

        - Up to 20MIPS throughput at 20MHz

        - On-chip 2-cycle multiplier 

    3. High-endurance non-volatile memory segment

        - 16/32/64/128KBytes of in-system self-programmable Flash program memory 

        - 512/1K/2K/4KBytes EEPROM

        - 1/2/4/16KBytes Internal SRAM

        - Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

        - Data retention: 20 years at 85°C / 100 years at 25°C

        - Optional boot code segment with independent lock bits

        - Software security programming lock

    4. Atmel QTouch® library support

        - Capacitive touch buttons, sliders and wheels

        - QTouch and QMatrix acquisition

        - Up to 64 sensing channels

    5. JTAG (IEEE std. 1149.1 Compliant) interface

        - JTAG compliant boundary scan capability

        - Extensive on-chip debug support

        - Program flash, EEPROM, fuses and lock bits via JTAG interface

    6. Peripheral functions

        - Two 8-bit timer/counters with independent prescaler and compare modes

        - One/two 16-bit timer/counter with independent prescaler, compare mode and capture mode

        - Real-time counter with independent oscillator

        - Six PWM channels

        - 8-channel, 10-bit ADC

        - Byte-oriented two-wire serial interface

        - Two programmable serial USARTs

        - Master/Slave SPI serial interface

        - Programmable watchdog timer with separate on-chip oscillator

        - On-chip analog comparator

        - Interrupt and wake-up on pin change

    7. Special microcontroller features

        - Power-on reset and programmable brown-out detection

        - Internally calibrated RC oscillator

        - External and internal interrupt sources

        - Six sleep modes: Idle, ADC Noise Reduction, Power Save, Power Down, Standby and Extended Standby

    8. I/O and packaging

        - 32 programmable I/O lines

        - 40-pin PDIP, 44-pin TQFP, 44-pad VQFN/QFN/MLF

        - 44-pad DRQFN

3. Capacitive touch sensing

The Atmel QTouch library provides an easy-to-use solution for implementing touch-sensitive interfaces on most Atmel AVR microcontrollers. The QTouch library includes support for QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR microcontroller. This is done by using a simple set of APIs to define touch channels and sensors, and then calling the touch-sensing API to retrieve channel information and determine touch sensor state.

4. ALU - Arithmetic Logic Unit

The high-performance AVR ALU is directly connected to all 32 general-purpose working registers. Arithmetic operations between general purpose registers or between registers and immediate values take place in a single clock cycle. ALU operations fall into three broad categories—arithmetic, logical, and bit functions. Some implementations of this architecture also provide a powerful multiplier that supports signed/unsigned multiplication and fractional formats.

5. Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and separate reset vectors have separate program vectors in program memory space. All interrupts are assigned individual enable bits that must be written to logic 1 along with the global interrupt enable bits in the status register to enable interrupts. Depending on the value of the program counter, interrupts may be automatically disabled when the boot lock bits BLB02 or BLB12 are programmed. This feature improves software security. The lowest addresses in the program memory space are defined by default as reset and interrupt vectors. The list also prioritizes the different interrupts. The lower the address, the higher the priority. RESET has the highest priority, and Next is INT0 - External Interrupt Request 0. The interrupt vector can be moved to the beginning of the boot. The flash section is implemented by setting the IVSEL bits in the MCU Control Register (MCUCR). When an interrupt occurs, the global interrupt enable I bit is cleared and all interrupts are disabled. User software can write a logic 1 to the I bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. When the return from interrupt instruction (RETI) is executed, the I bit is automatically set to execute. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program counter points to the actual interrupt vector to execute the interrupt handler, and the hardware clears the corresponding interrupt flag. Interrupt flags can also be

6. SRAM data memory

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The first 4,352 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory and the next 4,096 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Zregister. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the Atmel