ATSAMD20J18A-AN

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com

1. Operating Conditions

    1. 1.62V – 3.63V, -40°C to +85°C, DC up to 48 MHz

    2. 1.62V – 3.63V, -40°C to +105°C, DC up to 32 MHz

    3. 2.7V – 3.63V, -40°C to +125°C Extended Temperature with compliance to AEC-Q100, DC up to 32MHz

2. Core

    1. Arm®Cortex®-M0+ CPU running at up to 48 MHz

        – Single-cycle hardware multiplier

3. Memories

    1. 16/32/64/128/256 KB in-system self-programmable Flash

    2. 2/4/8/16/32 KB SRAM

4. System

    1. Power-on Reset (POR) and Brown-out Detection (BOD)

    2. Internal and external clock options with 48 MHz Digital Frequency Locked Loop (DFLL48M)

    3. External Interrupt Controller (EIC)

    4. Up to 16 external interrupts

    5. One non-maskable interrupt

    6. Two-pin Serial Wire Debug (SWD) programming, test and debugging interface

5. Low-Power

    1. Idle and Stand-by Sleep modes

    2. SleepWalking peripherals

6. Peripherals

    1. 8-channel Event System

    2. Up to eight 16-bit Timer/Counters (TC), configurable as:

        – One 16-bit TC with two compare/capture channels

        – One 8-bit TC with two compare/capture channels

        – One 32-bit TC with two compare/capture channels, by using two TCs

    3. 32-bit Real Time Counter (RTC) with clock/calendar function

    4. Watchdog Timer (WDT)

    5. CRC-32 generator

    6. Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:

        – USART with full-duplex and single-wire half-duplex configuration

        – Inter-Integrated Circuit (I2C) up to 400 kHz

        – Serial Peripheral Interface (SPI)

    7. One 12-bit, 350 ksps Analog-to-Digital Converter (ADC) with up to 20 channels

        – Differential and single-ended input

        – 1/2x to 16x programmable gain stage

        – Automatic offset and gain error compensation

        – Oversampling and decimation in hardware to support 13-bit, 14-bit, 15-bit, or 16-bit resolution

    8. 10-bit, 350 ksps Digital-to-Analog Converter (DAC)

    9. Two Analog Comparators (AC) with Window Compare function

  10. Peripheral Touch Controller (PTC)

        – Up to 256-channel capacitive touch and proximity sensing

7. I/O

    1. Up to 52 programmable I/O pins

8. Packages

    1. 64-pin TQFP, VQFN

    2. 64-ball UFBGA (not available in grades Extended Temperature and AEC-QA100)

    3. 48-pin TQFP, VQFN

    4. 45-ball WLCSP (not available in grades Extended Temperature and AEC-QA100)

    5. 32-pin TQFP, VQFN

    6. 27-ball WLCSP (not available in grades Extended Temperature and AEC-QA100)

9. Peripheral Power Consumption

    1. Operating conditions

        – VVDDIN = 3.3 V

    2. Oscillators

        – XOSC (crystal oscillator) stopped

        – XOSC32K (32 kHz crystal oscillator) running with external 32 kHz crystal

        – OSC8M at 8 MHz

    3. Clocks 

        – OSC8M used as main clock source

        – CPU, AHB, and APBn clocks undivided

    4. The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge

        – All other AHB clocks stopped

    5. The following peripheral clocks running: PM, SYSCTRL

        – All other peripheral clocks stopped

    6. I/Os are inactive with internal pull-up

    7. CPU in IDLE0 mode

    8. Cache enabled

    9. BOD33 disabled

10. start of the clock

After power-up, the device is set to its initial state and remains reset until power to the entire device stabilizes. After the power supply stabilizes, the device will use a 1MHz clock. This clock comes from the 8MHz internal oscillator (OSC8M), which is divided by 8 and used as the clock source for general purpose clock generator 0. Universal Clock Generator 0 is the main clock for the Power Manager (PM). Some synchronous system clocks are active, allowing software execution. See the Clock Mask Registers section in PM – Power Manager for a list of operating default peripheral clocks. The running synchronous system clock is undivided by default and receives a 1MHz clock through general purpose clock generator 0. Other general purpose clocks are disabled except GCLK_WDT, which is used by the watchdog timer (watchdog).

11. External real-time oscillator

The low frequency crystal oscillator is optimized for use with 32.768 kHz watch crystals. When selecting a crystal, the load capacitance and the crystal's equivalent series resistance (ESR) must be considered. Both values are specified by the crystal supplier. The SAM D20 oscillator is optimized for very low power consumption, so the user must pay close attention while choosing a crystal. Maximum ESR recommendations for 9 pF and 12.5 pF crystals. The Low Frequency Crystal Oscillator provides internal load capacitance crystal oscillator characteristics with typical values provided in Table 32 kHz. This internal load capacitor and PCB capacitor can use less than 12.5 pF load capacitance without external capacitors.

12. External Reset Circuit

The external Reset circuit is connected to the RESET pin when the external Reset function is used. The circuit is not necessary when the RESET pin is not driven low externally by the application circuitry. The reset switch can also be removed, if a manual reset is not desired. The RESET pin itself has an internal pull-up resistor, hence it is optional to add any external pull-up resistor. A pull-up resistor makes sure that the reset does not go low and unintentionally cause a device reset. An additional resistor has been added in series with the switch to safely discharge the filtering capacitor, that is, preventing a current surge when shorting the filtering capacitor, which again can cause a noise spike that can have a negative effect on the system.

13. Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization Ready interrupt can be used to signal when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY=1, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled.

14. Sleep Mode Operation

The run in the Standby bit in the Control A register controls the behavior of the ADC during Standby Sleep mode. When CTRLA.RUNSTDBY = 0, the ADC is disabled during sleep, but maintains its current configuration. When CTRLA.RUNSTDBY = 1, the ADC continues to operate during sleep. When CTRLA.RUNSTDBY = 0, the analog blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system returns from sleep. When CTRLA.RUNSTDBY = 1, any enabled ADC interrupt source can wake-up the CPU, except the OVERRUN interrupt.. While the CPU is sleeping, ADC conversion can only be triggered by events.