CDCLVP111RHBR

Due to market price fluctuations, if you need to purchase or consult the price. You can contact us or emial to us:   sales@allicdata.com

Clock/Timing - Clock Buffers, Drivers, is an application field of CDCLVP111RHBR. This device can provide a low cost, good performance solution for clock and timing terminal applications, such as clock distribution, clock synthesis, clock distribution buffer, clock multiplexer and etc, by means of LVDS (Low Voltage Differential Signaling) level shifting and buffer amplification. The working principle of CDCLVP111RHBR mainly contains two stages, the LVDS level shifting stage, the buffer amplification stage.

LVDS Level shifting stage

This stage is the core of the LVDS protocol, and it provides the LVDS conversion from the logic level voltage input data, commonly using 3.3V or 5V logic levels, to the LVDS sub-400mV output range. Thecomparator provides the two identical differential signals with amplified difference between them of the input voltage, with a sub-400mV differential output. In the CDCLVP111RHBR, the LVDS conversion is done by an output stage with a differential voltage swing of 400mV peak-to-peak; but to provide the correct voltage level, a reference voltage is necessary.

The reference or bias voltage is generated by an on-chip band gap reference, so no external reference is needed. Therefore, the CDCLVP111RHBR voltage output operation depends on the reference voltage (Vref) even if no input voltage is present. This feature eliminates the need for external clock impulses to maintain the output synchronization.

Buffer Amplification Stage

The LVDS level shifting stage is followed by the buffer amplification stage. This stage provides the clock regeneration from the low LVDS level signal to the logic levels, both 3.3V and 5V, with low output jitter and wide output duty cycle range. The buffer for the clock output can be driven in parallel with up to four outputs to reduce the signal impedance and signal loss. The duty cycle of the outputs is adjustable from 0-80 % using the external resistors.

The CDCLVP111RHBR guarantees a 50/50 output duty cycle and a matching skew between outputs over the entire operating temperature range.On the buffer amplification stage, a self-calibration algorithm is used in order to reduce the output-to-output skew, particularly on heavy capacitive loaded situations. This algorithm adjusts the voltage swing of the buffer output to re-establish a 50/50 duty cycle when the output load is changed.

Conclusion

CDCLVP111RHBR application field is Clock Buffers, Drivers which provides a low cost, good performance solution nearly all clock and timing terminal applications. It depends on the reference voltage (Vref), even if no input voltage is present, and self-calibration algorithm is used in order to reduce the output-to-output skew. With the clock LVDS level shifting stage provides the LVDS conversion from the logic level to the LVDS sub-400mV output range, followed by the buffer amplification stage providing clock regeneration from the low LVDS signal level to the logic levels, it is a great solution for clock applications.

The specific data is subject to PDF, and the above content is for reference