CDCV857BGQLR

CDCV857BGQLR is an highly integrated programmable clock generator designed to generate up to 10 independent low skew outputs. It is part of the clock/timing family and classified as clock generators, PLLs and frequency synthesizers. In this article, the application field and working principle of CDCV857BGQLR will be discussed.

Application Field

CDCV857BGQLR can be used in various applications such as storage, Network Interface Cards (NICs), CPU/GPU, Ethernet, PCIe, SAS/SATA speed switches, QSFP/SFP+, video clock generators, and TV/display related applications. It has been optimized for jitter, low power and flexibility to support next generation high-speed interfaces. It provides up to 10 clock outputs and has up to eight differential reference inputs.

Working Principle

The core of CDCV857BGQLR is its Integrated Clock Generator (ICG) that implements a PLL based architecture to generate low jitter clock frequency signals. It controls the operation of clock outputs according to the reference signals through a Digital Lock Detection (DLD) and a Band Gap Reference (BGR) regulator. DLD consists of an analog phase-frequency detector (PFD), an analog chargepump, a digital voltage controlled oscillator (VCO), and a digital divider.

The ICG uses the reference input to setup the desired clock frequency on the VCO. The charge pump loop of the PLL is used to adjust the VCO frequency until it matches the input reference frequency. Signals from the VCO are then divided by the digital divider to generate low jitter signals at the frequency set by the reference inputs. The generated clock signals are then fed to the BGR regulator which acts as an output buffer, to prepare the signals for routing to the clock output pins for driving external loads.

The output buffers are easily configurable by a few registers that the user can program to adjust the output setup, skew and jitter conditions. CDCV857BGQLR employs a programmable clocking source selector that allows the user to define which clock source will be used for each output. This enables the IC to support multiple clock sources. It also includes a power management mode feature which provides the ability to sequentially enable/disable outputs according to the user-defined sequence. This power saving feature reduces the current consumption when the outputs are not actively used.

Conclusion

CDCV857BGQLR is a highly integrated programmable clock generator designed to generate up to 10 independent low skew outputs. It can be used in various applications such as storage, Network Interface Cards (NICs), CPU/GPU, Ethernet, PCIe, SAS/SATA speed switches, QSFP/SFP+, video clock generators, and TV/display related applications. Its core is an Integrated Clock Generator (ICG), which implements a PLL based architecture to generate low jitter clock frequency signals, and several features such as Programmable clocking source selector, Digital Lock Detection (DLD) and Band Gap Reference (BGR) regulator provide further clocksource flexibility.