CDCVF310PWRG4

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The CDCVF310PWRG4 is a wide frequency range clock buffer/driver for low voltage low system power applications. It combines low voltage differential signaling (LVDS) and two additional outputs to drive the clock input of the FGPAs or CPLDs configured to run at a lower VDD than the source signal. The device boosts the input signal regeneratively to ensure reliable signal transmission over a wide signal range. With an integrated clock generator and spread spectrum frequency modulation, the CDCVF310PWRG4 ensures low system power and signal integrity.

This device is suitable for clock signal synchronization, signal distribution, and clock multi-channel fan-out applications in automotive, industrial and communications systems. This device allows up to four clock and data outputs to be driven simultaneously and supports three different output frequencies.

CDCVF310PWRG4 has four outputs (two odd, two even) configureable as input data lines, as pulse-width-modulated constant voltage output drivers, or as clock/data distribution drivers.

The CDCVF310PWRG4 buffer is a low-voltage, low-power clock/data fan-out buffer designed to receive a wide-range input clock and data signals and output them as a set of low-voltage, low-power clock/data signals.

The input clock is first divided by a 1:4 fan out and then buffered with a configurable, low-power clock buffer. The signal stay within the predefined voltage range as set by the output level control pins. An input signal range of 2 V to 5.75 V is supported with an input signal rise and fall time of 5 ns.

The CDCVF310PWRG4 supports three different output frequency ranges: 0-250 MHz, 0-500 MHz and 0-2 GHz. The maximum transfer rate of the output stages is 2.5 Gbps. The device includes internal pull-up and pull-down output current and supports spread-spectrum frequency modulation with frequencies in the range of 0-6 MHz and amplitudes up to 1%.

The CDCVF310PWRG4 buffers are provided in a 12-pin PDIP with 1.27 mm pitch and in a 48-pin LLP (low-profile leadless package) package with 1.0 mm pitch. The device provides an additional +0.75 V output in the LLP package. The LLP package is RoHS compliant.

The CDCVF310PWRG4 gives engineers the ability to drive multiple clock outputs from a single source for low voltage and low power applications. The device supports three output frequencies and spread-spectrum frequency modulation to reduce system EMI. The large input signal range and fast propagation delay make the CDCVF310PWRG4 a reliable choice for clock signal synchronization, signal distribution, and clock multi-channel fan-out applications.

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