DS1270AB-70#

Series:	--
Packaging:	Tube
Part Status:	Active
Memory Type:	Non-Volatile
Memory Format:	NVSRAM
Technology:	NVSRAM (Non-Volatile SRAM)
Memory Size:	16Mb (2M x 8)
Write Cycle Time - Word, Page:	70ns
Access Time:	70ns
Memory Interface:	Parallel
Voltage - Supply:	4.75 V ~ 5.25 V
Operating Temperature:	0°C ~ 70°C (TA)
Mounting Type:	Through Hole
Package / Case:	36-DIP Module (0.600", 15.24mm)
Supplier Device Package:	36-EDIP
Base Part Number:	DS1270AB

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Memory DS1270AB-70#

The DS1270AB-70# is a widely used memory device that can be applied in a variety of applications. This device is used widely due to its ability to perform data read and write operations quickly and reliably.This device is a descendent of the widely used DS1260A family of memories. It consists of a 70-bit serial interface, a 128-bit parity error-checking bus, and a local memory array designed to eliminate the costly overhead associated with higher speed data transfers. The local memory array is composed of a 16-bit, 4 Mbit NMOS SRAM and a secondary 8-bit, 2 Mbit Flash RAM.The device has been designed to be a low cost solution for applications requiring high performance memory access. It supports up to 256 address lines, enabling up to 65,536 words of data to be addressable. The data is transferred over the 16-bit bus in two 8-bit, 8-bit packages. This data is available from a secondary port allowing the device to access data from any non-volatile cache the host system has.The working principle of the device is based on RAM and SRAM chips. RAM chips store and transform data, while SRAM chips store and control the access of data to the device. The data is accessed via the 128-bit error-checking bus. This bus has been designed to reduce the chances of error during data access by incorporating some parity check bits.The local memory array is organized into groups of four columns, each with 16 data blocks. Data access is organized with each column being allocated a specific word and each bit being mapped to the memory address. The local memory array is further divided into four “planes”, each containing two “columns” of eight bits each of data. This organization allows for fast access of data through the extensive use of multiplexing.The bus system is organized in a similar fashion, with one bus being used to provide read requests, another to provide write requests, another to accept write response data, and another to issue read response data.The device also supports a low cost, low-power standby mode which allows it to remain in low power consumption until it is ready to accept a read or write request from the host system.Overall the DS1270AB-70# is a fantastic device for any system requiring fast and reliable memory access. Its combination of memory access and bus organization makes it a perfect choice for high performance applications.

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