DS8500-JND+

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1. Description

The DS8500-JND+ is a single-chip modem with Highway Addressable Remote Transducer (HART) capabilities. It has been fully tested and verified and has received a HART® Certificate of Registration. The device integrates the modulation and demodulation of the 1200Hz/2200Hz FSK signal, has very low power consumption, and needs only a few external components due to the integrated digital signal processing. The input signal is sampled by an analog-to-digital converter (ADC), followed by a digital filter/demodulator. This architecture ensures reliable signal detection in noisy environments. The output digitalto-analog converter (DAC) generates a sine wave and provides a clean signal with phase-continuous switching between 1200Hz and 2200Hz. Low power is achieved by disabling the receive circuits during transmit and vice versa. The DS8500 is ideal for low-power process control transmitters.

2. Features

    1. Single-Chip, Half-Duplex Modem Overlays 1200bps FSK Digital Communication on Top of Installed 4mA– 20mA Current Loop Infrastructure

    2. Digital Signal Processing Provides Reliable Input Signal Detection in Noisy Conditions

    3. Standard Component 3.6864MHz Crystal Reduces System Cost

    4. Fully Tested and Verified as a HART-Registered Modem IC

    5. Integrated Solution Requires Minimal Power and Space

       - 2.7V to 3.6V Operating Voltage

       - 285μA (max) Current Consumption

       - Space-Saving, 5mm x 5mm x 0.8mm, 20-Pin TQFN Package

       - Few External Components Required

3. Applications

    1. 4mA–20mA Loop-Powered Transmitters for Temperature, Pressure, Flow, and Level Measurement

    2. HART Multiplexers

    3. HART Modem Interface Connectivity

4. Pin Configuration

5. Pin Description

6. Functional Description

The DS8500-JND+ modem chip consists of a demodulator, carrier detect, digital filter, ADC for input signal conversion, a modulator and DAC for output signal generation, and receive and transmit state machine blocks to perform the HART communication. The Block Diagram illustrates the interface between various blocks of circuitry. The input HART signal’s noise interference is attenuated by a one-pole highpass filter that is external to the chip; the attenuated signal is digitized by the ADC and filtered by the receive state machine. The transmit state machine modulates the input to the HART-compliant signal with the help of the modulator and the DAC.