DS90LV012ATMFX

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DS90LV012ATMFX is an Enhanced, Single-Channel Low Voltage Differential Signaling (LVDS) Transceiver for serial data transmission applications. It is designed to support data rates up to 200 Mbps (100 Mbps with double-data rate). The LVDS system introduced a high bit-rate serial output interface with low power and electromagnetic compatibility (EMC) due to its transformer-less balanced output driver, eliminating common-mode noise source and reducing radiated emissions. The DS90LV012ATMFX is a perfect choice for sophisticated high-speed point-to-point interface applications or as a member of high-speed backplane systems.

Application Field:

The DS90LV012ATMFX is usually applied for the high data rate, low power and flexibility, working in the following areas:

• High-speed point-to-point interconnect applications
• High-speed backplane or switched fabrics
• High-speed cable interconnections
• High-speed connection between processors and I/O devices

Working Principle:

• The DS90LV012ATMFX is a differential serial data transmitter and receiver.
• The transmitter accepts an 8-bit TTL/CMOS parallel data input, buffers and uses a Low Skew Clock line to select and clock data to the output driver.
• The output panel includes two LVDS pairs (never more than two independent channels) that are labeled A and B. While A and B are functionally similar, the functional pin pair inputs have a slightly different arrangement.
• The differential data signals from each output differential pair changes from low to high when going from logic 0 to logic 1. The differential output voltage is primarily determined by the transmitted supply voltage (VCC).

The DS90LV012ATMFX is a high-performance, low-power, single-channel LVDS transceiver for interfacing a host processor to a LVDS compatible network. It utilizes a class-A, transformer-less output driver to reduce power consumption and provide low-skew, high-signal-strength output signals. The device incorporates low-skew skewclock fanout buffers, auto-direction sensing, and an internal fail-safe protocol to ensure reliable data communication.

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