DS90LV028ATLD Integrated Circuits (ICs)

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The DS90LV028ATLD is a high-speed interface solution designed to improve the performance and capabilities of devices with data rates up to 20 megabits per second. It is a low-voltage LVDS driver/receiver (transceiver) designed for use in systems requiring energy-efficient data and clock transmission between boards and components. The DS90LV028ATLD extends the benefits of LVDS architecture to the high-speed, point-to-point application field.

Features

The DS90LV028ATLD is an efficient, high-speed driver/receiver capable of delivering data rates up to 20 Mbps. The solutions low power consumption is ideal for portable and low power system designs. The driver is a for 10-bit parallel data sources, and can interface with other logic families such as LVTTL and LVCMOS. The receiver is for 10-bit parallel LVDS data/strobe and SMA clock/data pairs, and includes a selectable data input where both 3.3 V and 2.5 V supply levels are supported.

Applications

The DS90LV028ATLD is ideal for high-speed point-to-point transmission applications such as:

• High-speed connections between external devices and logic ICs, such as connecting microprocessors with DRAMs.
• Multi-board interconnects and computer busses.
• Video applications.

Working Principle

The DS90LV028ATLD functions as a low-voltage LVDS driver/receiver. The driver receives LVTTL/LVCMOS type logic signals and converts them to low-voltage differential signals. The receiver then re-converts the differential signal back to LVTTL/LVCMOS level voltage levels.

The driver has two differential outputs, OA and OB. Each output has a dedicated control line, OEnA and OEnB. Whenever either of the control lines is logic high, the respective differential output is in a high impedance state and the output is disabled. The output OA is driven by logic levels on the A0–A9 inputs whilst the output OB is driven by logic levels on the B0–B9 inputs. By setting OEnA and OEnB high, the outputs can be disabled.

The receiver contains two low-voltage differential data inputs, IOA and IOB. A differential pair, SMA+, SMA– is also provided as a clock input. IOA and IOB accept differential LVDS data/strobe pairs and The SMA+/– input is used to provide a clock reference. Both data inputs are protected by diodes to independent power supplies. This allows the receiver to accept differential data from either a 3.3 V or 2.5 V LVDS driver.

The receiver includes two outputs, DOA and DOB, for logic level output signals. DOA and DOB are TTL/CMOS compatible, which allows the use of logic families other than LVTTL/LVCMOS.

In summary, the DS90LV028ATLD is an efficient, high-speed interface solution capable of data rates of up to 20 megabits per second. The transceiver is ideal for the high-speed point-to-point connection, and is designed to support both 3.3 V and 2.5 V single-ended and differential signaling.

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