EPC16QI100N

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1. Description

The Altera EPC device is a single device with high speed and advanced configuration solution for highdensity FPGAs. The core of an EPC device is divided into two major blocks—a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more than one Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed using the external flash interface after the FPGA configuration is complete.

2. Features

    1. Single-chip configuration solution for Altera®ACEX® 1K, APEX® 20K , APEX II, Arria®GX, Cyclone®, Cyclone II, FLEX® 10K , Mercury®, Stratix® II, and Stratix II GX devices

    2. Contains 4-, 8-, and 16-Mb flash memories for configuration data storage

    3. On-chip decompression feature almost doubles the effective configuration density

    4. Standard flash die and a controller die combined into single stacked chip package

    5. External flash interface supports parallel programming of flash and external processor access to unused portions of memory

    6. Flash memory block or sector protection capability using the external flash interface

    7. Supported in EPC4 and EPC16 devices

    8. Page mode support for remote and local reconfiguration with up to eight configurations for the entire system

    9. Compatible with Stratix series remote system configuration feature

  10. Supports byte-wide configuration mode fast passive parallel (FPP) with an 8-bit data output per DCLK cycle

  11. Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs

  12. Pin selectable 2-ms or 100-ms power-on reset (POR) time

  13. Configuration clock supports programmable input source and frequency synthesis

  14. Multiple configuration clock sources supported (internal oscillator and external clock input pin)

  15. External clock source with frequencies up to 100 MHz

  16. Internal oscillator defaults to 10 MHz and you can program the internal oscillator for higher frequen‐cies of 33, 50, and 66 MHz

  17. Clock synthesis supported using user programmable divide counter

  18. Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA (UFBGA) packages

  19. Vertical migration between all devices supported in the 100-pin PQFP package

  20. Supply voltage of 3.3 V (core and I/O)

  21. Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification

  22. Supports ISP using Jam Standard Test and Programming Language (STAPL)

  23. Supports JTAG boundary scan

  24. The nINIT_CONF pin allows private JTAG instruction to start FPGA configuration

  25. Internal pull-up resistor on the nINIT_CONF pin always enabled

  26. User programmable weak internal pull-up resistors on nCS and OE pins

  27. Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines

  28. Standby mode with reduced power consumption