EPC16UI88N

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1. Description

The Altera EPC device is a single device with high speed and advanced configuration solution for highdensity FPGAs. The core of an EPC device is divided into two major blocks—a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more than one Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed using the external flash interface after the FPGA configuration is complete.

2. Features

    1. Single-chip configuration solution for Altera®ACEX®1K, APEX®20K , APEX II, Arria® GX, Cyclone®, Cyclone II, FLEX®10K , Mercury®, Stratix®II, and Stratix II GX devices

    2. Contains 4-, 8-, and 16-Mb flash memories for configuration data storage

    3. On-chip decompression feature almost doubles the effective configuration density

    4. Standard flash die and a controller die combined into single stacked chip package

    5. External flash interface supports parallel programming of flash and external processor access to unused portions of memory

    6. Flash memory block or sector protection capability using the external flash interface

    7. Supported in EPC4 and EPC16 devices

    8. Page mode support for remote and local reconfiguration with up to eight configurations for the entire system

    9. Compatible with Stratix series remote system configuration feature

  10. Supports byte-wide configuration mode fast passive parallel (FPP) with an 8-bit data output per DCLK cycle

  11. Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs

  12. Pin selectable 2-ms or 100-ms power-on reset (POR) time

  13. Configuration clock supports programmable input source and frequency synthesis

  14. Multiple configuration clock sources supported (internal oscillator and external clock input pin)

  15. External clock source with frequencies up to 100 MHz

  16. Internal oscillator defaults to 10 MHz and you can program the internal oscillator for higher frequen‐ cies of 33, 50, and 66 MHz

  17. Clock synthesis supported using user programmable divide counter

  18. Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA (UFBGA) packages

  19. Vertical migration between all devices supported in the 100-pin PQFP package

  20. Supply voltage of 3.3 V (core and I/O)

  21. Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification

  22. Supports ISP using Jam Standard Test and Programming Language (STAPL)

  23. Supports JTAG boundary scan

  24. The nINIT_CONF pin allows private JTAG instruction to start FPGA configuration

  25. Internal pull-up resistor on the nINIT_CONF pin always enabled

  26. User programmable weak internal pull-up resistors on nCS and OE pins

  27. Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines

  28. Standby mode with reduced power consumption

3. FPGA Configuration

FPGA configuration is managed by the configuration controller chip. This process includes reading configuration data from the flash memory, decompressing the configuration data, transmitting configura‐ tion data using the appropriate DATA[ ] pins, and handling error conditions. After POR, the controller determines the user-defined configuration options by reading its option bits from the flash memory. These options include the configuration scheme, configuration clock speed, decompression, and configuration page settings. The option bits are stored at flash address location 0x8000 (word address) and occupy 512-bits or 32-words of memory. These options bits are read using the internal flash interface and the default 10 MHz internal oscillator. After obtaining the configuration settings, the configuration controller chip checks if the FPGA is ready to accept configuration data by monitoring the nSTATUS and CONF_DONE signals. When the FPGA is ready, the controller begins data transfer using the DCLK and DATA[ ] output pins. The controller selects the configuration page to be transmitted to the FPGA by sampling its PGM[2..0] pins after POR or reset. The function of the configuration unit is to transmit decompressed data to the FPGA, depending on the configuration scheme. The EPC device supports four concurrent configuration modes, with n = 1, 2, 4, or 8 . The value n = 1 corresponds to the traditional PS configuration scheme. The values n = 2, 4, and 8 correspond to concurrent configuration of 2, 4, or 8 different PS configuration chains, respectively. Additionally, the FPGA can be configured in FPP mode, where eight bits of DATA are clocked into the FPGA per DCLK cycle. Depending on the configuration bus width (n), the circuit shifts uncompressed configuration data to the valid DATA[n] pins. Unused DATA[] pins drive low. In addition to transmitting configuration data to the FPGAs, the configuration circuit is also responsible for pausing configuration whenever there is insufficient data available for transmission. This occurs when the flash read bandwidth is lower than the configuration write bandwidth. Configuration is paused by stopping the DCLK to the FPGA, when waiting for data to be read from the flash or for data to be decompressed. This technique is called “Pausing DCLK”. The EPC device flash-memories feature a 90-ns access time (approximately 10 MHz). Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[ ], at 10 MHz). However, the configuration speeds supported by Altera FPGAs are much higher and translate to high configuration write bandwidths. For example, 100-MHz Stratix FPP configuration requires data at the rate of 800 Mbps . This is much higher than the 160 Mbps the flash memory can support and is the limiting factor for configuration time. Compression increases the effective flash-read bandwidth as the same amount of configuration data takes up less space in the flash memory after compression. Since Stratix configuration data compression ratios are approximately two, the effective read bandwidth doubles to about 320 Mbps. Finally, the configuration controller also manages errors during configuration. A CONF_DONE error occurs when the FPGA does not de-assert its CONF_DONE signal within 64 DCLK cycles after the last bit of configu‐ ration data is transmitted. When a CONF_DONE error is detected, the controller pulses the OE line low, which pulls the nSTATUS signal low and triggers another configuration cycle. A cyclic redundancy check (CRC) error occurs when the FPGA detects corruption in the configuration data. This corruption could be a result of noise coupling on the board such as poor signal integrity on the configuration signals. When this error is signaled by the FPGA , the controller stops configuration. If the Auto-Restart Configuration After Error option is enabled in the FPGA, it releases its nSTATUS signal after a reset time-out period and the controller attempts to reconfigure the FPGA. After the FPGA configuration process is complete, the controller drives the DCLK pin low and the DATA[ ] pins high. Additionally, the controller tri-states its internal interface to the flash memory, enables the weak internal pull-ups on the flash address and control lines, and enables bus-keep circuits on flash data lines. The following sections describe the different configuration schemes supported by the EPC device—FPP, PS, and concurrent configuration schemes.