FIN212ACGFX Integrated Circuits (ICs)

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Serializers, deserializers, and serializer/deserializers (serdes) are the fundamental building blocks of digital systems. Serializers and deserializers convert digital signals into a bitstream, while serializer/deserializers undertake the additional step of combining data and clock signals into a single serial data stream.

FIN212ACGFX is a high speed serializer/deserializer designed to interface with FPGA devices. It is capable of aggregating up to four channels of FPGA-generated data into a single serialized data stream, then simultaneously clock-rate and format that data for transfer over parallel or high-speed, point-to-point channels. FIN212ACGFX is designed to operate at up to 16.5 Gbps for up to four channels, but is run at faster speeds where one-channel operation is utilized.

The serializer portion of the FIN212ACGFX processes the digital serial data, collects digital timing signals, reformats the data, and restructures the digital interface with the serial data. The FIN212ACGFX deserializer performs the opposite role, reassembling the digital serial data, reconstructing digital timing signals, and returning the data to a structured digital interface that can be readily read by FPGA devices.

The FIN212ACGFX’s design includes several features that aid in its ability to perform the serialization and deserialization of data. First and foremost is the integrated clock synthesis and Phase-Locked Loop (PLL) circuitry. This allows FIN212ACGFX to adaptively lock its reference clock and sample rate to an incoming data stream from a variety of external sources. This can substantially reduce the complexity of the design, as there is no need to generate and maintain separate clock and data signals. FIN212ACGFX also has on-chip de-skew circuitry, which resides between the data deserializer and the FPGA interface. This helps to ensure that the deserialized data is synchronously presented to the FPGA in the same order as it was received.

Another important design feature of the FIN212ACGFX is the Cable Length Detection feature, which measures the length of the cable connected to the FPGA device and adjusts the data transfer rate accordingly. This helps to ensure that at longer cable lengths, there is a prolonged signal life and greater signal integrity. FIN212ACGFX also has signal-lane scrambling, which forces systematic differences in the data stream, to spread signal peaks across all signal lanes. This helps to reduce the risk of simultaneous switching noise (SSN) or signal-induced jitter, which typically arise in high-bandwidth applications. Furthermore, FIN212ACGFX includes an optimized FPGA interface with a 120x36 register-addressable dual data port interconnect (DDBI) interface.

FIN212ACGFX can be used in a variety of applications, including network interfaces, memory interface designs, and high-speed communications links. The deserializer/serializer can be implemented as a data receiver, supporting both clock and data rate variability, or as a data transmitter, providing even greater data rate variability than existing designs. The FIN212ACGFX is also suitable for streaming applications with up to 16.5 Gbps data throughput and eight channels of synchronized transmit and receive streams.

FIN212ACGFX is ideal for applications that need to improve throughput and minimize latency in data transfers over long distances. The integrated PLL circuitry allows for clock and data recovery at distances of up to ten meters, making it ideal for applications where cable length variables are a consideration. Additionally, the low power consumption, small footprint, and high speed performance provided by the FIN212ACGFX make it an ideal choice for FPGA-based systems.

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