HLS10

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High-level synthesis (HLS) is a method of computer-assisted system-level design that allows a user to rapidly design and prototype a digital system using a high-level, abstract description. By providing functionality that is conceptually close to the input specification, HLS tools can greatly reduce the time required to create a complex digital system. HLS has become increasingly popular over the last decade, as it has enabled users to quickly and accurately develop a range of application-specific digital systems.

While HLS can be applied to many different application domains including image processing, digital signal processing, embedded control, and processor-based systems, this article focuses on the domain of wireless communications. This application field is characterised by the need for rapidly creating and prototyping complex digital systems that are suitable for use in physical and virtual environments. HLS provides a streamlined approach to developing such systems, allowing users to quickly design, prototype, and deploy a range of wireless communication solutions.

At the core of HLS lies its ability to efficiently transform high-level source code descriptions of hardware designs into optimized target code. This transformation is facilitated by the use of sophisticated techniques, such as algorithm-specific hardware (ASH) and multiprocessor architectures (MPA) that allow for the efficient use of resources without compromising performance.

ASH is a methodology that enables the design of sophisticated algorithms that can be used to solve complex problems in a highly optimised manner. This is achieved by dividing the problem into smaller sub-problems and implementing each sub-problem as a distinct hardware block. The resulting blocks can then be efficiently integrated to form an optimised algorithm. While ASH is a powerful tool for efficiently solving complex problems, its use requires significant expertise.

MPA is a technique used to create highly optimised multiprocessor systems. It involves partitioning a given problem into multiple sub-problems and designing separate processing elements to perform each sub-problem in parallel. By harnessing the power of multiple processors, MPA can reduce the time required to solve a given problem compared to a single processor approach. For example, an 8-core MPA system is capable of solving certain problems up to eight times faster than a single processor system. Furthermore, MPA systems are more power efficient than single processor systems, making them more suitable for low-power applications.

In addition to these two core techniques, HLS also includes a number of other powerful features. For example, HLS tools provide the ability to specify and verify the behavior of designs using assertion-based verification (ABV). ABV enables a user to quickly and accurately verify that the hardware design meets the specified requirements. Additionally, HLS provides the ability to leverage RTL-level synthesis, which provides more control over the design process and ensures that the generated hardware meets the desired performance goals.

HLS is also well suited for creating accelerated systems. It provides the ability to leverage a range of specialized architectures, including programmable logic such as FPGAs and ASICs, for custom hardware solutions. Additionally, HLS tools can also leverage the power of GPUs for fast, application-specific acceleration. Overall, HLS provides a comprehensive and efficient approach to system-level design, allowing users to quickly develop digital systems that meet their needs.

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