LMX2595RHAT RF/IF and RFID

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1. Description

The LMX2595RHAT high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 20 GHz. An integrated doubler is used for frequencies above 15 GHz. The high-performance PLL with figure of merit of –236 dBc/Hz and highphase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.The LMX2595 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2595 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.The output drivers within LMX2595 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

2. Features

    1. 10-MHz to 20-GHz output frequency

    2. –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier

    3. 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)

    4. Programmable output power

    5. PLL key specifications

        – Figure of merit: –236 dBc/Hz

        – Normalized 1/f noise: –129 dBc/Hz

        – High phase detector frequency

           – 400-MHz integer mode

           – 300-MHz fractional mode

        – 32-bit fractional-N divider

    6. Remove integer boundary spurs with programmable input multiplier

    7. Synchronization of output phase across multiple devices

    8. Support for SYSREF with 9-ps resolution programmable delay

    9. Frequency ramp and chirp generation ability for FMCW applications

  10. < 20-µs VCO calibration speed

  11. 3.3-V single power supply operation

3. Applications

    1. 5G and mm-Wave wireless infrastructure

    2. Test and measurement equipment

    3. Radar

    4. MIMO

    5. Phased array antennas and beam forming

    6. High-speed data converter clocking (supports JESD204B)

4. Feature Description

    1. Reference Oscillator Input

        The OSCin pins are used as a frequency reference input to the device. The input is high impedance and requires AC-coupling caps at the pin. A CMOS clock or XO can drive the single-ended OSCin pins. Differential clock input is also supported, making it easier to interface with high-performance system clock devices such as TI’s LMK series clock devices. As the OSCin signal is used as a clock for the VCO calibration, a proper reference signal must be applied at the OSCin pin at the time of programming FCAL_EN.

    2. OSCin Doubler (OSC_2X)

        The OSCin doubler allows one to double the input reference frequency up to 400 MHz. This doubler adds minimal noise and is useful for raising the phase detector frequency for better phase noise and also to avoid spurs. When the phase-detector frequency is increased, the flat portion of the PLL phase noise improves.

    3. Pre-R Divider (PLL_R_PRE)

        The Pre-R divider is useful for reducing the input frequency so that the programmable multiplier (MULT) can be used to help meet the maximum 250-MHz input frequency limitation to the PLL-R divider. Otherwise, it does not have to be used.

    4. Programmable Multiplier (MULT)

        The MULT is useful for shifting the phase-detector frequency to avoid integer boundaryrs. The multiplier allows a multiplication of 3, 4, 5, 6, or 7. Be aware that unlike the doubler, the programmable multiplier degrades the PLL figure of merit. This only would matter, however, for a clean reference and if the loop bandwidth was wide.

    5. Post-R Divider (PLL_R)

        The Post-R divider can be used to further divide down the frequency to the phase detector frequency. When it is used (PLL_R > 1), the input frequency to this divider is limited to 250 MHz.

    6. State Machine Clock

        The state machine clock is a divided down version of the OSCin signal that is used internally in the device. This divide value is 1, 2, 4, or 8, and is determined by CAL_CLK_DIV programming word (described in the Programming section). This state machine clock impacts various features like the lock detect delay, VCO calibration, and ramping. The state machine clock is calculated as fsmclk = fOSC / 2 CAL_CLK_DIV.

    7. PLL Phase Detector and Charge Pump

        The phase detector compares the outputs of the Post-R divider and N-divider, and generates a correction current corresponding to the phase error until the two signals are aligned in-phase. This charge pump current is software programmable to many different levels, allowing modification of the closed-loop bandwidth of the PLL. 

5. Application Information

    1. OSCin Configuration

        The OSCin supports single-ended or differential clocks. There must be a AC-coupling capacitor in series before the device pin. The OSCin inputs are high-impedance CMOS with internal bias voltage. TI recommends putting termination shunt resistors to terminate the differential traces (if there are 50-Ω characteristic traces, place 50-Ω resistors). The OSCin and OSCin* side should be matched in layout. A series AC-coupling capacitors should immediately follow OSCin pins in the board layout, then the shunt termination resistors to ground should be placed after.

    2. OSCin Slew Rate

        The slew rate of the OSCin signal can impact the spurs and phase noise of the LMX2595 if it is too low. In general, a high slew rate and a lower amplitude signal, such as LVDS, can give best performance.

    3. RF Output Buffer Power Control

        The OUTA_PWR and OUTB_PWR registers can be used to control the output power of the output buffers. The setting for optimal power may depend on the pullup component, but is typically around 50. The higher the setting, the higher the current consumption of the output buffer.

    4. RF Output Buffer Pullup

        The choice of output buffer components is very important and can have a profound impact on the output power. If using a single-ended output, a pullup is required, and the user can put a 50-Ω resistor after the capacitor.