LPC1224FBD48/101,1

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1. Description

The LPC1224FBD48/101,1 extend NXP's 32-bit ARM microcontroller continuum and target a wide range of industrial applications in the areas of factory and home automation. Benefitting from the ARM Cortex-M0 Thumb instruction set, the LPC122x have up to 50 % higher code density compared to common 8/16-bit microcontroller performing typical tasks. The LPC122x also feature an optimized ROM-based divide library for Cortex-M0, which offers several times the arithmetic performance of software-based libraries, as well as highly deterministic cycle time combined with reduced flash code size. The ARM Cortex-M0 efficiency also helps the LPC122x achieve lower average power for similar applications. The LPC122x operate at CPU frequencies of up to 45 MHz.They offer a wide range of flash memory options, from 32 kB to 128 kB. The small 512-byte page erase of the flash memory brings multiple design benefits, such as finer EEPROM emulation, boot-load support from any serial interface and ease of in-field programming with reduced on-chip RAM buffer requirements. The peripheral complement of the LPC122x includes a 10-bit ADC, two comparators with output feedback loop, two UARTs, one SSP/SPI interface, one I2C-bus interface with Fast-mode Plus features, a Windowed Watchdog Timer, a DMA controller, a CRC engine, four general purpose timers, a 32-bit RTC, a 1 % internal oscillator for baud rate generation, and up to 55 General Purpose I/O (GPIO) pins.

2. Feature

    1. Processor Core

        - ARM Cortex-M0 processor, operating frequency up to 45 MHz (wait state from flash memory) or 30 MHz (zero wait state from flash memory). LPC122x scored more than 45 in the CoreMark CPU performance benchmark test, which is equivalent to 1.51/MHz.

        - ARM Cortex-M0 has a built-in Nested Vectored Interrupt Controller (NVIC).

        - Serial Wire Debug (SWD).

        - System tick timer

    2. Memory

        - Up to 8 kB SRAM.

        - Up to 128 kB of on-chip flash programming memory.

        - In-system programming (ISP) and in-application programming (IAP) are performed by the on-chip bootloader software.

        - Including ROM-based 32-bit integer division routines.

    3. Clock generation unit

        - A crystal oscillator with an operating range of 1 MHz to 25 MHz.

        - Adjust the 12 MHz internal RC (IRC) oscillator to 1% accuracy, and can optionally be used as the system clock.

        - PLL allows the CPU to run at the maximum CPU speed without using a high-frequency crystal oscillator. It can be run by the system oscillator or the internal RC oscillator.

        - The clock output function with frequency divider can reflect the system oscillator clock, IRC clock, main clock and watchdog clock.

        - Real Time Clock (RTC).

    4. Digital Peripherals

        - Mini DMA controller with 21 channels.

        - CRC engine.

        - Two UARTs with fractional baud rate generation and internal FIFO. Support RS-485 and modem UART and IrDA standard UART.

        - SSP/SPI controller, with FIFO and multi-protocol functions.

        - I2C bus interface supports complete I2C bus specification and fast mode Plus, with a data rate of 1 Mbit/s, with multiple address recognition and monitoring modes. The I2C bus pins have programmable interference filters.

        - Up to 55 general-purpose I/O (GPIO) pins with programmable pull-up resistors, open-drain mode, programmable digital input interference filter and programmable input inverter.

        - Programmable output drivers on all GPIO pins. Four pins support high-current output drivers.

        - All GPIO pins can be used as edge and level sensitive interrupt sources.

        - Four general-purpose counters/timers with four capture inputs and four match outputs (32-bit timers) or two capture inputs and two match outputs (16-bit timers).

        - Window Watchdog Timer (WWDT); IEC-60335 Type B certification.

    5. Analog Peripherals

        - An 8-channel, 10-bit ADC.

        - Two highly flexible analog comparators. The comparator output can be programmed to trigger a timer match signal or simulate 555 timer behavior.

    6. Power

        - Three low-power modes: sleep, deep sleep and deep power-down.

        - The processor wakes up from deep sleep mode by using the startup logic of port 12 pins.

        - The processor wakes up from deep power-down and deep sleep modes through RTC.

        - The power-down detection has three independent thresholds, each of which is used for interruption and forced reset.

        - Power-on reset (POR).

        - Integrated PMU (Power Management Unit).

    7. The unique device serial number is used for identification.

    8. 3.3V power supply.

    9. Available in 64-pin and 48-pin LQFP packages.

3. Application

    1. Electronic Metering

    2. Lighting

    3. Industrial networking

    4. Alarm system

4. Pin configuration

5. Pin description

All pins except power pins can have multiple functions. The pin function is selected through the IOCON register of the pin in the IOCONFIG module. this The multiplexing function (see Table 4) includes counter/timer input and output, UART receiving, sending and control functions, as well as serial wire debugging functions. For each pin, the default function and the reset state of the pin are listed first.

6. Package overview