LPC2478FBD208,551

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1. Describe

Driven by the ARM7TDMI-S core, the LPC2478 microcontroller designed by NXP Semiconductors is a highly integrated microcontroller suitable for a wide variety of applications requiring advanced communications and high-quality graphics. The LPC2478 microcontroller has 512 kB of on-chip high-speed flash. The flash includes a special 128-bit wide memory interface and accelerator architecture that enables the CPU to execute sequential instructions from flash at a maximum system clock rate of 72 MHz. This feature is only available on the LPC2000 ARM microcontroller family. The LPC2478 has a real-time debug interface including JTAG and embedded trace, and can execute 32-bit ARM and 16-bit Thumb instructions. The LPC2478 microcontroller contains an LCD controller, a 10/100 Ethernet media access controller (MAC), a USB full-speed device with 4 kB endpoint RAM, four UARTs, two controller area network (CAN) channels/ Host/OTG controller, one SPI interface, two synchronous serial ports (SSP), three I2C interfaces and one I2S interface. Supporting this set of serial communication interfaces are the following functional components; an on-chip 4 MHz internal oscillator, 98 kB total RAM including 64 kB local SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for general purpose DMA, 2 kB Battery-backed SRAM and an external memory controller (EMC). These features make the device ideal for portable electronics and point-of-sale (POS) applications. Various 32-bit timers, a 10-bit ADC, 10-bit DAC, two PWM units and up to 160 fast GPIO lines complement the many serial communication controllers, multi-function clock functions and memory functions. The LPC2478 connects 64 GPIO pins to a hardware- based Vectored Interrupt Controller (VIC), allowing external inputs to generate edge-triggered interrupts. All these features make the LPC2478 particularly suitable for industrial control and medical systems.

2. Features

    1. ARM7TDMI-S processor, running at up to 72 MHz.

    2. 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.

    3. 98 kB on-chip SRAM includes:

        - 64 kB of SRAM on the ARM local bus for high performance CPU access.

        - 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

        - 16 kB SRAM for general purpose DMA use also accessible by the USB.

        - 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.

    4. LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays.

        - Dedicated DMA controller.

        - Selectable display resolution (up to 1024  768 pixels).

        - Supports up to 24-bit true-color mode.

    5. Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.

    6. EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM.

    7. Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

    8. General Purpose DMA (GPDMA) controller on AHB that can be used with the SSP, I2S-bus, and SD/MMC interface as well as for memory-to-memory transfers.

    9. Serial Interfaces:

        - Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB.

        - USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller.

        - Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.

        - CAN controller with two channels.

        - SPI controller.

        - Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.

        - Three I2C-bus interfaces (one with open-drain and two with standard port pins).

        - I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.

  10. Other peripherals:

        - SD/MMC memory card interface.

        - 160 General purpose I/O pins with configurable pull-up/down resistors.

        - 10-bit ADC with input multiplexing among 8 pins.

        - 10-bit DAC.

        - Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input.

        - Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count input.

        - RTC with separate power domain. Clock source can be the RTC oscillator or the APB clock.

        - 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off.

        - WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.

  11. Single 3.3 V power supply (3.0 V to 3.6 V).

  12. 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the system clock.

  13. Four reduced power modes: idle, sleep, power-down and deep power-down.

  14. Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources.

  15. Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).

  16. Two independent power domains allow fine tuning of power consumption based on needed features.

  17. Each peripheral has its own clock divider for further power saving. These dividers help reduce active power by 20 % to 30 %.

  18. Brownout detect with separate thresholds for interrupt and forced reset.

  19. On-chip power-on reset.

  20. On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.

  21. On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.

  22. Boundary scan for simplified board testing.

  23. Versatile pin function selections allow more possibilities for using on-chip peripheral functions.

  24. Standard ARM test/debug interface for compatibility with existing tools.

  25. Emulation trace module supports real-time trace.

3. Application

    1. Industrial control

    2. Medical system

    3. Portable electronic products

    4. Point-of-sale (POS) devices

4. Pin configuration