MC100E211FNR2

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The MC100E211FNR2 is part of the Clock and Timing lineup for ON Semiconductor and is a differential driver with a low power 2:1 clock and data multiplexer. This device is designed primarily for clocking and multiplexing data in digital system applications where fast switching and low power dissipation is paramount.

The MC100E211FNR2 has a power up enable/disable feature that allows the user to delay the initialization of the device while other system components are being powered up. This feature minimizes switching transients that could otherwise interfere with the clock and data buses.

The MC100E211FNR2 contains two 2-input multiplexers which in turn have four 3-STATE outputs, each pair complementary. The multiplexers, in conjunction with the two external select signals SELA and SELB, permit data to be multiplexed at a rate of 2:1 at either the rising or falling edge, or completely bypassed.

The MC100E211FNR2 has two clock inputs. The clock for each multiplexer is asynchronous, but the two external select signals (SELA and SELB) are synchronous to the input clock. The device contains two non-overlap circuits, one on each output clock, to ensure high frequency stability when multiplexing the data between the two multiplexers.

The MC100E211FNR2 clock/data multiplexer employs an internal high speed pulse-shaping circuit and a clock-synchronous power-up control circuit. The device also has automatic phase-locked loop (PLL) detection circuitry capable of recognizing and correcting phase errors of up to 90 degrees in the system clock.

The MC100E211FNR2 is an ideal buffer solution in communication, cellular and instrumentation systems that require reliable clock distribution with fast switching speed and low power consumption. It is also well-suited for use in HDTV/DTV receivers, baseband processors, image processing equipment and communications networks.

This device is available in two surface-mount packages, the 48-pin TSSOP (10x20 mm) and the 28-pin SOIC (8x14 mm). The device offers an economical solution for the multiplexing of data in high-speed, high-frequency applications. It has the ability to multiplex data from two channels at a rate of 2:1 or completely bypass it. The device also features non-overlap switching and pulse-shaping that helps reduce harmonic distortion in digital communications.

The MC100E211FNR2 is designed to reduce power consumption while providing a wide range of high performance timing applications. It is ideal for communications, cell phone, and instrumentation system applications that require reliable clock distribution right out of the box. It is a cost-effective, low power solution for clock and data multiplexing applications.

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