MC100EL13DWG

Series:	100EL
Packaging:	Tube
Part Status:	Obsolete
Type:	Fanout Buffer (Distribution)
Number of Circuits:	2
Ratio - Input:Output:	1:3
Differential - Input:Output:	Yes/Yes
Input:	ECL, PECL
Output:	ECL, PECL
Frequency - Max:	1GHz
Voltage - Supply:	4.2 V ~ 5.7 V
Operating Temperature:	-40°C ~ 85°C
Mounting Type:	Surface Mount
Package / Case:	20-SOIC (0.295", 7.50mm Width)
Supplier Device Package:	20-SOIC
Base Part Number:	MC100EL13

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The MC100EL13DWG is a clock buffer, or clock divider, that can facilitate the transmission of clock signals through noisy environments, reduce EMI susceptibility and eliminate the need for external pull-ups or pull-downs. It is used in a wide range of applications, such as telecommunications, networking, digital audio and industrial control.The MC100EL13DWG is a low-skew, low-jitter clock buffer. It has two main functionalities – buffering and division. By reducing the number of buffered stage and the accumulated clock skew, it can provide precise synchronization between multiple clock sources. Additionally, the division functionality allows the user to configure the output clock to be a desired ratio of the input clock. This ratio can range from 1:1 to 31:1, with the flexibility to adjust both the “high” and “low” periods of the output clock.The MC100EL13DWG is designed for use in an array of different applications. It can be used in audio streaming applications, where synchronized playback of digital audio streams is necessary. It can also be used in data processing systems, to reliably divide clock rates and feed them to energy-efficient systems with no extra power consumption. Additionally, in digital video transmission systems, the clock buffer can be used to reduce interference and reduce the power consumption of data-dependent systems.The working principle of the MC100EL13DWG is quite simple. It takes an input clock signal, reduces the input-to-output clock skew and divides the input frequency by a desired ratio to produce an output frequency. The device has two types of outputs – a differential output for buffering the input clock, and a single-ended output for divided clock signals. Furthermore, it has an asynchronous boundary scan mode, enables users to select the clock division ratio by controlling the output enable pins.To use the MC100EL13DWG, the user must select the desired clock division ratio, connect the input clock signal, and enable the desired output. Once the setup is complete, the clock buffer will reliably propagate the incoming clock signals with minimal skew and jitter. Additionally, if the output enable pins of the device are configured according to the desired clock division ratio, the MC100EL13DWG will divide the clock signal and produce the corresponding output frequency.Overall, the MC100EL13DWG is a versatile clock buffer that can be used in a variety of different applications. It can reduce the number of buffered stage and the accumulated clock skew, allowing multiple clock sources to synchronize precisely. Additionally, it can reliably divide incoming clock signals according to the desired output frequency. With its ability to reduce EMI susceptibility, it is an ideal choice for numerous applications in telecommunications, networking, digital audio and industrial control.

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