MC100EP56DWG

Series:	100EP
Packaging:	Tube
Part Status:	Active
Type:	Differential Digital Multiplexer
Circuit:	2 x 2:1
Independent Circuits:	1
Current - Output High, Low:	--
Voltage Supply Source:	Dual Supply
Voltage - Supply:	±3 V ~ 5.5 V
Operating Temperature:	-40°C ~ 85°C
Mounting Type:	Surface Mount
Package / Case:	20-SOIC (0.295", 7.50mm Width)
Supplier Device Package:	20-SOIC
Base Part Number:	100EP56

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Logical signal transfer devices such as multiplexers, decoders and switches are used to manage logic signals in numerous electrical and electronic systems. The introduction of MC100EP56DWG into the field of logic signal switching devices further expands their application potential and range. The MC100EP56DWG utilizes principles of differential input/output (I/O) pairs called ECL pairs to process switching functions of two channels of 8-bits each. This differential pair type of device simplifies circuit design associated with the logic signal transfer of multiple ECL levels. Additionally, the device offers a 50-ohm differential output termination structure, which is situated between the output node and the associated matched transistor. In this way, the output stage is effectively isolated from undesirable parasitic effects. The MC100EP56DWG offers a power-saving feature that allows the chip to go into a static “Sleep” mode. This mode causes the entire chip to be disabled, saving power. To use this feature, the chip must first be enabled by the Wake Up signal. Once the Chip is active, a Pause signal can also be utilized to conserve power without resetting the logic states between the two channels. Multi-Level Logic (MLL) circuits offer the advantage of improved power consumption and less noise than process-based logic systems. The MC100EP56DWG integrates six stages of HUBB-compliant MLL technology with two independent channels of 8-bits each for switching applications. The device utilizes bi-directional non-blocking data paths, which allow the user to choose either a single data-bit or a full eight data-bits to be used as the switching output. The MC100EP56DWG is designed to accept ECL-type logic levels on its inputs as logic “High” and logic “Low”. The output, in turn, requires a threshold of Voh to be triggered, which is equivalent to the high “1” and low “0” logic levels in a CMOS-based logic system. This makes the device an ideal choice for switching logic signals between logic families. The MC100EP56DWG provides several output configuration options to suit the switching justification requirements of the system. It offers a “Fast Turn-Off” option for increased system power savings, as well as a TTL/CMOS output pin for a “Fast Turn-On” application. A forced Power Down option has also been added to suit under-voltage protection applications, and the device is protected from the effects of latch-up current flows. The use of the MC100EP56DWG in logic circuit applications provides a solution for simplifying signal transfer between logic families. Its multi-stage logic allows for fast, reliable switching of digital logic signals, while its low power draw and sleep mode feature make it ideal for power-conscious designs. Additionally, with its wide range of output configuration options, the MC100EP56DWG multiplexer/decoder/switch device is an effective choice for use in almost any digital system.

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