MK9173-15CS08

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The MK9173-15CS08 is a digital PLL-based clock generator for sdram clock and ac timing control designed according to the requirements of DIMM chipsets. It has an internal crystal oscillator, frequency synthesizer design and two low-skew differential outputs for driving DDR devices. It offers a wide variance in output frequencies from 166 MHz - 200 MHz, and is capable of providing both PECL outputs and Zero-delay outputs. The device\'s PLL circuit divides the input logic clock frequency by a programmable factor of up to 128. It features a wide range of install frequencies, selectable synchronous or asynchronous inputs, a low power consumption, a low output skew, a programmable output slew rate, and is available in either a RoHS compliant PLCC-32 package or a RoHS compliant QFP-32 package.

The MK9173-15CS08 is an ideal fit for a variety of applications, such as high performance computing, storage systems, military systems, telecommunications and network application. This device is suitable for advanced memory interface designs, mobile systems and digital audio/video traffic. It can also be used in the generation of advanced clock signals for the demanding needs of high speed applications and for general purpose clock distribution.

Working Principle: The clock generator is designed around a digital PLL, which is used to generate the clock frequency output correctly. The digital PLL has two major components, the phase detector (PD) and the voltage-controlled oscillator (VCO). The PD is used to detect the difference in the phase between the reference clock and the system clock. It then produces a voltage which is used by the VCO to adjust the frequency until they match. This ensures that the output clock frequency is the same as the reference clock frequency. The reference clock frequency is programmed using an external counter frequency divider. The VCO produces the new clock frequency which is then divided using output divide circuitry to generate the desired output frequency.

The clock generator also has a phase-locked loop (PLL) loop filter, which is used to reduce phase noise by providing damping and increase cycle to cycle jitter immunity. It also ensures that the VCO is properly tuned and does not become unstable during operation, which can cause clock generation problems. The device also has an integrated on-chip power-on reset circuit which guarantees that the device is reset correctly during power up.

The output of the device is two low-skew differential outputs for driving DDR devices, which are programmable to be synchronous or asynchronous. The output also has a programmable slew rate and output voltage, which can be adjusted for different operating conditions. The device is also equipped with a power-down mode which can be used to reduce power consumption in standby mode.

In summary, the MK9173-15CS08 is a digital PLL based clock generator designed specifically for sdram clock frequencies and ac timing controlling. It offers a wide range of install frequencies, selectable synchronous or asynchronous inputs, low power consumption, low output skew and a programmable output slew rate. Its two low-skew differential outputs for driving DDR devices make it an ideal choice for high performance computing, storage systems, military systems, telecommunications, and network applications.

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