| Allicdata Part #: | NBSG11BAHTBG-ND |
| Manufacturer Part#: |
NBSG11BAHTBG |
| Price: | $ 0.00 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | ON Semiconductor |
| Short Description: | IC CLK BUFFER 1:2 12GHZ 16FCBGA |
| More Detail: | Clock Fanout Buffer (Distribution) IC 1:2 12GHz 16... |
| DataSheet: |  NBSG11BAHTBG Datasheet/PDF |
| Quantity: | 1000 |
| 1 +: | 0.00000 |
Specifications
| Series: | -- |
| Packaging: | Tape & Reel (TR) |
| Part Status: | Obsolete |
| Type: | Fanout Buffer (Distribution) |
| Number of Circuits: | 1 |
| Ratio - Input:Output: | 1:2 |
| Differential - Input:Output: | Yes/Yes |
| Input: | CML, LVCMOS, LVDS, LVTTL, NECL, RSNECL, PECL |
| Output: | RSECL, RSNECL, RSPECL |
| Frequency - Max: | 12GHz |
| Voltage - Supply: | 2.375 V ~ 3.465 V |
| Operating Temperature: | -40°C ~ 70°C |
| Mounting Type: | Surface Mount |
| Package / Case: | 16-LBGA, FCBGA |
| Supplier Device Package: | 16-FCBGA (4x4) |
| Base Part Number: | NBSG11 |
Description
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NBSG11BAHTBG is a low jitter, low skew, PECL-buffered, 2.5V CMOS clock buffer and fanout device, which can be widely adopted in clock/ timing systems. This article will demonstrate the applications of NBSG11BAHTBG and its working principle, in order to provide a better understanding of its uses.Applications
The NBSG11BAHTBG can be deployed in the clock/timing systems that involve the synchronization and routing of clock signals. For example, it can be used to solve the timing challenges in high frequency data switching systems, digital and analog subsystems, chip-to-chip communication, as well as generating accurate system clocks and distributing them among logic/memory devices. Additionally, the very low jitter, <4ps typical for the NBSG11BAHTBG, and its enable and disable features provide a great benefit for synchronous clock distribution applications.The NBSG11BAHTBG can also be applied in network clock systems, such as the SyncE, where it serves as the clock source in a PLL (Phase Locked Loop) or as the divider to generate lower frequency “sync” clock signals. When serving as the synchronization source, NBSG11BAHTBG fanout devices can be used to generate simultaneous outputs that are phase coherent.Other applications where the NBSG11BAHTBG can be used include delay-line systems and FPGA-based systems where timing requirements are particularly tight and require synchronous clock distribution and clock recovering from a primary clock. Also, the device is especially suitable for printing system designs, where it can be used to control the printing engine to ensure the perfect synchronization of each print head.Working Principle
The NBSG11BAHTBG consists of four buffered outputs and operates on a 2.5V power supply. The buffer utilizes a low noise, low phase-shift PECL driver to send out Clock A and its inversion, Clock A /, on the dual outputs. Two further outputs, also driven by a PECL driver, produce tightly matched clock pair B and B /. This buffer also provides an enable input, which can be used to make all the four outputs unable to transmit data.The buffered outputs generated by the NBSG11BAHTBG are able to drive 50-ohm loads, or multiple fanout buffers as long as they do not exceed the normal limits of fanout numbers specified in datasheet. Furthermore, the buffer has fine-tuned output impedance and input impedance matching to ensure that the transmitted clock signal is same in both quality and quantity.The NBSG11BAHTBG can be programmed to function as a single-ended device, with Clock A and its inversion being the output pair, or as a differential device, with the previously mentioned Clock A and B being the output pairs. This type of flexibility and the PECL drive capability make this buffer an ideal choice for digital and mixed-signal systems.Conclusion
The NBSG11BAHTBG is an ideal choice for clock/timing systems where jitter, skew, and low noise performance are required. It is suitable for use in network clock systems, delay-line systems and FPGA-based systems. The buffered outputs generated by this buffer can drive 50-ohm loads or multiple fanout buffers and its enable input enables users to cut off the clock signal transmission. By understanding the applications and working principles of this clock buffer, users can make proper use of it in their clock/timing systems.The specific data is subject to PDF, and the above content is for reference
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