PCA9698DGG,512

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1. Describe

The PCA9698DGG,512 provides 40-bit parallel input/output (I/O) port expansion for I2C bus applications divided into 5 groups of 8 I/Os. The outputs are capable of sourcing 10 mA and sinking 25 mA from a 5 V supply with a total package load of 1 A and can directly drive 40 LEDs. Any of the 40 I/O ports can be configured as input or output. The PCA9698DGG,512 is the first GPIO device in the new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequencies (up to 1 MHz) and longer, denser bus operations (up to 4000 pF). The device is fully configurable: output ports can be programmed as totem pole or open drain, logic state can be changed on acknowledge (group change) or stop command (global change), and each input port can be masked to prevent it from uninterrupting Generated when their state changes, and when read by the system host, the logic state of I/O data can be reversed. An open-drain interrupt output pin (INT) allows an input pin to be monitored and set every time one or more input ports (unless masked) change. The output enable pin (OE) tri-states any I/O selected as an output and can be used as an input signal to blink or dim an LED (PWM frequency > 80 Hz and change duty cycle). The "GPIO All Call" command allows multiple advanced GPIOs to be programmed simultaneously, even if they have different I2C bus addresses. This allows optimized code programming When multiple devices need to be programmed with the same instructions or when all outputs need to be turned on or off at the same time. The device ID is hardcoded in PCA9698DGG,512, allowing the system host to read manufacturer, part type and revision information. The SMBus Alert feature allows the SMBALERT pins of multiple devices with this feature to be connected together to form a wired-AND signal and used with the SMBus Alert Response Address. An internal power-on reset (POR) or hardware reset pin (RESET) initializes the 40 I/Os as inputs. Three address select pins configure one of 64 slave addresses. The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over the -40 °C to +85 °C industrial temperature range.

2. Features

    1. 1 MHz Fast-mode Plus I2C-bus serial interface

    2. Compliant with I2C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)

    3. 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

    4. 40 configurable I/O pins that default to inputs at power-up

    5. Outputs:

        - Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink) with controlled edge rate output structure. Default to totem-pole on power-up.

        - Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be programmed to active HIGH through the I2C-bus. Defaults to OE on power-up.

        - Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time respectively. Defaults to Acknowledge on power-up.

    6. Inputs:

        - Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs

        - Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change

        - Polarity Inverter register allows inversion of the polarity of the I/O pins when read

    7. Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus ‘Alert Response Address’ sequence. Own slave address sent when sequence initiated.

    8. Active LOW Reset (RESET) input pin resets device to power-up default state

    9. GPIO All Call address allows programming of more than one device at the same time with the same parameters

  10. 64 programmable slave addresses using 3 address pins

  11. Readable Device ID (manufacturer, device type and revision)

  12. Designed for live insertion in PICMG applications

        - Minimize line disturbance (IOFF and power-up 3-state)

        - Signal transient rejection (50 ns noise filter and robust I2C-bus state machine)

  13. Low standby current

  14. −40 °C to +85 °C operation

  15. ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101

  16. Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

  17. Packages offered: TSSOP56, and HVQFN56

3. Application

    1. Server

    2. RAID system

    3. Industrial Control

    4. Medical equipment 

    5. PLC

    6. Cell Phone

    7. Game console

    8. Instrumentation and Test Measurements

4. Pin configuration