S9S12G128AMLF

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1. Describe

The S9S12G128AMLF family is a line of automotive-optimized 16-bit microcontrollers focused on low cost, high performance and low pin count. This series is designed to interface high-end 8-bit microcontrollers and high-performance 16-bit microcontrollers such as the MC9S12XS series. The MC9S12G family is aimed at communicating in general-purpose automotive applications requiring CAN or LIN/J2602. Typical examples of these applications include body controllers, occupant detection, door modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes. The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family, including error-correcting code (ECC) on flash memory, fast analog-to-digital converter (ADC), and frequency-modulated phase-locked loop (IPLL) for improved EMC performance. The MC9S12G family is optimized for smaller program memory down to 16k. To simplify customer use, it has a 4-byte erasable sector size EEPROM. The MC9S12G family offers all the benefits and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC and code size efficiency benefits currently enjoyed by users of NXP's existing 8- and 16-bit MCU families. Like the MC9S12XS family, the MC9S12G family runs 16-bit wide accesses to all peripherals and memory without wait states. The MC9S12G family is available in 100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP, and 20-pin TSSOP package options designed to maximize feature count, especially for lower pin count Package. In addition to the I/O ports available in each module, the other I/O ports are interrupt capable, allowing wake-up from stop or wait modes.

2. Feature

    1. S12 CPU core

    2. Up to 240 KB on-chip flash with ECC

    3. Up to 4 KB EEPROM with ECC

    4. Up to 11 KB of on-chip SRAM

    5. Phase Locked Loop (IPLL) Frequency Multiplier with Internal Filter

    6. 4–16 MHz amplitude controlled Pierce oscillator

    7. 1 MHz internal RC oscillator

    8. Timer Module (TIM) supports up to 8 channels, providing a range of 16-bit input capture, output compare, counter and pulse accumulator functions

    9. Pulse Width Modulation (PWM) module with up to eight 8-bit channels

  10. Up to 16-channel, 10- or 12-bit resolution successive approximation analog-to-digital converters (ADCs)

  11. Up to two 8-bit digital-to-analog converters (DACs)

  12. Up to one 5V analog comparator (ACMP)

  14. Up to three Serial Peripheral Interface (SPI) modules

  15. Up to three Serial Communication Interface (SCI) modules supporting LIN communication

  16. Up to one Multi-Scalable Controller Area Network (MSCAN) module (supports CAN protocol 2.0A/B)

  17. On-chip voltage regulator (VREG) to regulate input supply and all internal voltages

  18. Autonomous Periodic Interrupt (API)

  19. Precision fixed voltage reference for ADC conversions

  20. Optional reference voltage attenuator module to improve ADC accuracy

3. Pin configuration

4. Central Processing Unit (CPU)

    1. Full 16-bit datapath supports efficient arithmetic operations and high-speed math execution

    2. Includes many single-byte instructions. This allows for more efficient use of ROM space.

    3. Extensive index addressing capabilities, including:

        - use the stack pointer as the index register in all indexing operations

        - Use the program counter as an index register except in auto-increment/decrement mode

        - accumulator offset using A, B, or D accumulators

        - Automatic indexing of predecrement, preincrement, postdecrement and postincrement (from –8 to +8)

5. Port Integration Module (PIM)

    1. Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J, and AD when used as general purpose I/O

    2. Control registers are used to enable/disable pull-up devices and select pull-up/pull-down on ports T, S, M, P, J and AD on a per-pin basis

    3. Single control register to enable/disable pull devices on ports A, B, C, D, and E, per port and BKGD pin

    4. Control register to enable/disable open-drain (wired OR) mode on ports S and M

    5. Interrupt Flag Registers for Pin Interrupts on Ports P, J and AD

    6. Control registers for configuring IRQ pin operation

    7. Routing registers that support programmable signal redirection only in 20 TSSOP

    8. Routing registers that support programmable signal redirection only in the 100 LQFP package

    9. Factory preset package code register associated with the package in use, which can be written once after reset. Also Include bits to reprogram API_EXTCLK routing in all packages.

  10. Control register for free-running clock output

6. Serial Communication Interface Module (SCI)

    1. Up to three SCI modules

    2. Full-duplex or single-wire operation

    3. Standard mark/space non-return-to-zero (NRZ) format

    4. Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

    5. 13-bit baud rate selection

    6. Programmable character length

    7. Programmable polarity for transmitter and receiver

    8. Active edge receive wakeup

    9. Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602

7. Serial Peripheral Interface Module (SPI)

    1. Up to three SPI modules

    2. Configurable 8- or 16-bit data size

    3. Full-duplex or single-wire bidirectional

    4. Double-buffered transmit and receive

    5. Master or slave mode

    6. MSB-first or LSB-first shifting

    7. Serial clock phase and polarity options