S9S12G64AMLH

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1. Describe

The S9S12G64AMLH family is a family of automotive 16-bit microcontrollers designed for Low cost, high performance and low pin count. This family is designed to bridge high-end 8-bit Microcontrollers and high-performance 16-bit microcontrollers such as the MC9S12XS family. This The MC9S12G family targets general-purpose automotive applications requiring CAN or LIN/J2602 communication. Typical examples of these applications include body controllers, occupant detection, door Modules, Seat Controllers, RKE Receivers, Smart Actuators, Lighting Modules and Smart Junction Boxes. The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family, Includes error correcting code (ECC) on flash memory, fast analog-to-digital converter (ADC) and Frequency Modulated Phase Locked Loop (IPLL) for improved EMC performance. The S9S12G64AMLH family is optimized for smaller program memory down to 16k. simplify Customers use it with 4-byte erasable sector size EEPROM. The MC9S12G family offers all the advantages and efficiencies of a 16-bit MCU while maintaining low Cost, power, EMC and code size efficiency benefits NXP users currently enjoy Existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family runs 16-bit No need to wait for extensive access to all peripherals and memory. The MC9S12G series is available in 100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and Designed to maximize feature count, especially for lower pin count packages. Also Each module has I/O ports available, more I/O ports are interrupt capable, allowing Wake from stop or wait mode.

2. Feature

    1. S12 CPU core

    2. Up to 240 KB on-chip flash with ECC

    3. Up to 4 KB EEPROM with ECC

    4. Up to 11 KB of on-chip SRAM

    5. Phase Locked Loop (IPLL) Frequency Multiplier with Internal Filter

    6. 4–16 MHz amplitude controlled Pierce oscillator

    7. 1 MHz internal RC oscillator

    8. Timer Module (TIM) supports up to 8 channels, provides a range of 16-bit input capture, Output compare, counter and pulse accumulator functions

    9. Pulse Width Modulation (PWM) module with up to eight 8-bit channels

  10. Successive approximation analog-to-digital converters up to 16-channel, 10- or 12-bit resolution (ADC)

  11. Up to two 8-bit digital-to-analog converters (DACs)

  12. Up to one 5V analog comparator (ACMP)

  13. Up to three Serial Peripheral Interface (SPI) modules

  14. Up to three Serial Communication Interface (SCI) modules supporting LIN communication

  15. Up to one Multi-Scalable Controller Area Network (MSCAN) module (supports CAN protocol 2.0A/B)

  16. On-chip voltage regulator (VREG) to regulate input supply and all internal voltages

  17. Autonomous Periodic Interrupt (API)

  18. Precision fixed voltage reference for ADC conversions

  19. Optional reference voltage attenuator module to improve ADC accuracy

3. Pin configuration

4. 16-Bit Central Processor Unit (CPU)

    1. Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution

    2. Includes many single-byte instructions. This allows much more efficient use of ROM space.

    3. Extensive set of indexed addressing capabilities, including:

        — Using the stack pointer as an indexing register in all indexed operations

        — Using the program counter as an indexing register in all but auto increment/decrement mode

        — Accumulator offsets using A, B, or D accumulators

        — Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)

5. Port Integration Module (PIM)

    1. Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used as general-purpose I/O

    2. Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J and AD on per-pin basis

    3. Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis and on BKGD pin

    4. Control registers to enable/disable open-drain (wired-or) mode on ports S and M

    5. Interrupt flag register for pin interrupts on ports P, J and AD

    6. Control register to configure IRQ pin operation

    7. Routing register to support programmable signal redirection in 20 TSSOP only

    8. Routing register to support programmable signal redirection in 100 LQFP package only

    9. Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages.

  10. Control register for free-running clock outputs

6. Main External Oscillator (XOSCLCP)

    1. Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal

        — Current gain control on amplitude output

        — Signal with low harmonic distortion

        — Low power

        — Good noise immunity

        — Eliminates need for external current limiting resistor

        — Transconductance sized for optimum start-up margin for typical crystals

        — Oscillator pins can be shared w/ GPIO functionality

7. Internal Phase-Locked Loop (IPLL)

    1. Phase-locked-loop clock frequency multiplier

        — No external components required

        — Reference divider and multiplier allow large variety of clock rates

        — Automatic bandwidth control mode for low-jitter operation

        — Automatic frequency lock detector

        — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

        — Reference clock sources:

        — External 4–16 MHz resonator/crystal (XOSCLCP)

        — Internal 1 MHz RC oscillator (IRC)

8. Controller Area Network Module (MSCAN)

    1. 1 Mbit per second, CAN 2.0 A, B software compatible

        — Standard and extended data frames

        — 0–8 bytes data length

        — Programmable bit rate up to 1 Mbps

    2. Five receive buffers with FIFO storage scheme

    3. Three transmit buffers with internal prioritization

    4. Flexible identifier acceptance filter programmable as:

        — 2 x 32-bit

        — 4 x 16-bit

        — 8 x 8-bit

    5. Wakeup with integrated low pass filter option

    6. Loop back for self test

    7. Listen-only mode to monitor CAN bus

    8. Bus-off recovery by software intervention or automatically

    9. 16-bit time stamp of transmitted/received messages

9. Serial Communication Interface Module (SCI)

    1. Up to three SCI modules

    2. Full-duplex or single-wire operation

    3. Standard mark/space non-return-to-zero (NRZ) format

    4. Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

    5. 13-bit baud rate selection

    6. Programmable character length

    7. Programmable polarity for transmitter and receiver

    8. Active edge receive wakeup

    9. Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602

10. Serial Peripheral Interface Module (SPI)

    1. Up to three SPI modules

    2. Configurable 8- or 16-bit data size

    3. Full-duplex or single-wire bidirectional

    4. Double-buffered transmit and receive

    5. Master or slave mode

    6. MSB-first or LSB-first shifting

    7. Serial clock phase and polarity options