SI52112-B5-GM2R

Series:	--
Packaging:	Tape & Reel (TR)
Part Status:	Active
PLL:	Yes
Main Purpose:	PCI Express (PCIe)
Input:	Clock, Crystal
Output:	HCSL
Number of Circuits:	1
Ratio - Input:Output:	1:2
Differential - Input:Output:	No/Yes
Frequency - Max:	100MHz
Voltage - Supply:	2.97 V ~ 3.63 V
Operating Temperature:	-40°C ~ 85°C
Mounting Type:	Surface Mount
Package / Case:	10-WFDFN Exposed Pad
Supplier Device Package:	10-TDFN (3x3)

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Introduction

The SI52112-B5-GM2R is an application specific clock/timing device designed for a variety of clock and timing needs. The SI52112-B5-GM2R combines the high-performance of a low-power IDT 7 Series Integrated Buffer and the functionality of a PLL to offer a perfect solution for single or multiple clock tree applications. The device is applicable to many different high-speed communication and embedded computing applications, the device provides unprecedented levels of jitter performance and low power consumption in a compact package.

Features

The SI52112-B5-GM2R offers many distinct features which make it the optimal choice for a variety of clock/timing applications. These features include:

• Integrated PLL providing up to four outputs.
• Very low jitter performance.
• Very low power consumption.
• Low pin count.
• Small footprint.

Applications

TheSI52112-B5-GM2R is well suited for a variety of applications including networking, consumer electronics and consumer communication. This includes applications such as:

• 10 Gbps Ethernet applications
• Gigabit Ethernet applications
• USB 3.0 applications
• SATA 6Gb/s applications
• PCS/PMA applications
• OC-48 applications
• Serial RapidIO applications
• XAUI applications

The SI52112-B5-GM2R can also be used for high frequency clocks in FPGAs and ASICs, as well as a variety of embedded computing applications.

Working Principle

The SI52112-B5-GM2R features an integrated PLL that can generate up to four output clocks with very low jitter. The PLL is built using a technique called Phase Frequency Detector PFD and a Charge Pump Circuit, and it essentially works in the following way:

• The PFD monitors the differences in the rising and falling edges of the input and the reference clock.
• The PFD compares the edges and sends an appropriate signal to the charge pump circuit.
• The charge pump circuit produces a output current based on the PFD’s input.
• The output current is then used to drive the VCO.
• Finally, the VCO produces an output at the desired frequency.

Conclusion

The SI52112-B5-GM2R is an application specific clock/timing device designed for a variety of clock and timing needs. It combines the high-performance of a low-power IDT 7 Series Integrated Buffer and the functionality of a PLL to offer a perfect solution for single or multiple clock tree applications. The features of the SI52112-B5-GM2R, such as its very low jitter performance and low power consumption, make it an ideal choice for a variety of high-speed communication and embedded computing applications. Finally, its integrated PLL uses a PFD and a charge pump circuit to generate the desired outputs at very low jitter.

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