Allicdata Part #: | 296-5063-5-ND |
Manufacturer Part#: |
SN74ALS533ADW |
Price: | $ 2.46 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Texas Instruments |
Short Description: | IC D-TYPE LATCH TRI-ST 20-SOIC |
More Detail: | D-Type Transparent Latch 1 Channel 8:8 IC Tri-Stat... |
DataSheet: | SN74ALS533ADW Datasheet/PDF |
Quantity: | 1000 |
150 +: | $ 2.23835 |
Series: | 74ALS |
Packaging: | Tube |
Part Status: | Active |
Logic Type: | D-Type Transparent Latch |
Circuit: | 8:8 |
Output Type: | Tri-State |
Voltage - Supply: | 4.5 V ~ 5.5 V |
Independent Circuits: | 1 |
Delay Time - Propagation: | 6ns |
Current - Output High, Low: | 2.6mA, 24mA |
Operating Temperature: | 0°C ~ 70°C |
Mounting Type: | Surface Mount |
Package / Case: | 20-SOIC (0.295", 7.50mm Width) |
Supplier Device Package: | 20-SOIC |
Base Part Number: | 74ALS533 |
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SN74ALS533ADW is a 3.3V voltage compatible CMOS latch of the Logic - Latches family that offers very low power consumption. It is very suitable for interlocking or in applications that require address translation. SN74ALS533ADW contains two latches with input data of D and inverse input of DI, and each one of them is set with its own latch enable. It also has output enable (OE) and GND terminals. A latch ensures that data will be stored even when the clock signal is absent. Designed with TTL interface and CMOS output level, this low power latch is capable of working over wide temperature ranges and is available in a TSSOP16 package.
This device operates with an open collector output that is fully powered by a 3.3V power supply input. It requires to be enabled by a low input level to operate; thus, the EN pin is used to turn the latch on and off. When EN is at high level, the output is in quiescent state. However, when EN is at low level, the latch will be active.
When EN is at low level, DI will determine the logic state of the Q output. An active low output will be produced when DI is at high level, and an active high state will be produced when DI is at low level. When EN is in high level, the Q output is put into quiescent state regardless ofthe DI input. In addition, the output state for Q and its inverse can be held by configuring the OE pin to a low state. The OE pin can also be used to hold the output in a high impedance state to minimize the power consumption.
The main application fields of SN74ALS533ADW are programmable logic gates, data convertion and latch applications. As an interlocking device it requires minimum space and is not critical to data setup and hold time. Also SN74ALS533DW is suitable in applications that require address translation, like memory control. Thanks to its low power consumption, this device can be easily used in portable products such as cell phones and PDAs.
In conclusion SN74ALS533DW is a low power voltage compatible CMOS latch suitable for various applications including infomation memory control and programmable logic gates. With open collector output, 3.3V power supply, TTL interface and CMOS output level, SN74ALS533DW offers features like low power consumption, stable operation and wide temperature range that make it an ideal device for a wide range of applications.
The specific data is subject to PDF, and the above content is for reference
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