SN74LVT573PWR

Logic - Latches

The SN74LVT573PWR belongs to a family of advanced high speed CMOS latch circuits designed with positive-edge triggered flip flops incorporating proprietary noise/EMI reduction circuitries. As a result, the circuits efficiently eliminate metastable immune behavior caused by low pulse width operation. This product family is characterized by low power dissipation, wide operating voltage range (VCC = 1.65V ~ 3.6V) and high noise immunity.

Application Field

The SN74LVT573PWR latch has a wide variety of applications as a control function. Some typical uses include clock or enable enable signals, gated D latches, data storage elements and much more. This latch can also used to construct address decoders, data selectors/multiplexers, and other basic logic components.

This device is particularly suited for battery-powered equipment because of the CMOS’s excellent supply current characteristics. Additionally, the SN74LVT573PWR is a high performance device with short propagation delay times, high noise immunity and high-speed/low-power operation. This makes the SN74LVT573PWR perfect for modern high-speed logic systems.

Working Principle

The SN74LVT573PWR employs an edge triggered architecture wherein data present at the time of the falling edge of the Clock (CP) is transferred to the Outputs (Q and Q#) of the device. The latch is designed to hold data as long as VCC stays within its specified range. When reset by the /RESET0 pin, the latch will reset to a logic low state.

The SN74LVT573PWR latch has two positive-edge triggered flip flops, which are designed using two cross-coupled NAND gates. The outputs of the NAND gates, called Q and Q#, are the two latch outputs. When a rising edge is applied to the Clock input (CP), the gates will switch states, thus enabling the Q and Q# outputs to change according to the input data.

When the latch is not clocked (inactive state), the Q and Q# outputs are static and if VCC falls below the specified range, the latch will reset to the logic low state and the Q and Q# outputs will remain low until power is restored.