SPC5566MZP80R

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com

1. Describe

The MPC5566 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on Power Architecture embedded technology. This series of devices has many new features, combined with high-performance CMOS technology, which can significantly and significantly reduce the cMOS improve the performance of the MPC500 series. The device's host processor core complies with the Power Architecture Embedded category and is 100% user-mode compatible with the original PowerPC instruction set. Embedded architecture enhancements improve the performance of the cores also embedded The core applications additional instructions, including digital signal processing (DSP) instructions beyond the original PowerPC instruction set. The MPC5500 family of parts includes many new features that, combined with high-performance CMOS technology, significantly improve the performance of the MPC565 coress host' The MPC565 Also includes instruction set enhancements that allow vari able length encoding (VLE). This allows optional encoding of mixed 16-bit and 32-bit instructions. With this enhancement, the code size footprint can be significantly reduced. The MPC5566 has a two-level memory hierarchy. The fastest access is to the 32 kilobyte (KB) unified cache. The next level in the hierarchy contains 128 KB of on-chip internal SRAM and three megabytes (MB) of internal Flash. Internal SRAM and Flash memory hold instructions and data. The external bus interface is designed to support most standard memories for use with the MPC5xx family. The complex I/O timer functions of the MPC5566 are performed by two Enhanced Time Processor Unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware channels . The eTPU enhances the TPU by providing the following features: 24-bit timers, double-acting hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is programmed using a high-level programming language. The less complex timer functions of the MPC5566 are performed by the Enhanced Modular Input/Output System (eMIOS). The 24 hardware channels of eMIOS are capable of single-action, double-action, Pulse width modulation (PWM) and modulo counter operation. Motor control functions include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including Controller Area Network (FlexCAN), Enhanced Deserialization/Serial Peripheral (DSPI), and Enhanced Serial Communications Interface (eSCI). DSPI supports pin reduction with hardware serialization and deserialization of timer lanes and general-purpose input/output (GPIO) signals. The MCU has an on-chip enhanced queued dual analog-to -digital converter (eQADC). There are 40 channels. The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled by the SIU. External interrupt and reset control is also determined by the SIU. The internal multiplexer sub-block provides multiplexing of eQADC trigger sources, daisy-chain DSPI and external interrupt signal multiplexing. Fast Ethernet ( FEC) modules are RISC-based controllers that support 10 and 100 Mbps Ethernet/IEEE® 802.3 networks and are compatible with three different standard MAC (Media Access controller) PHY (physical) interface to the external Ethernet bus. FEC support 10 or 100 Mbps MII (Media Independent Interface) and 10 Mbps only seven-wire interface, which Uses a subset of MII signals. The upper 16 bits of the 32-bit External Bus Interface (EBI) are used for Connect to external Ethernet devices. The FEC contains built-in transmit and receive message FIFOs and DMA support.