SST26VF032B-104I/SM

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1. Describe

Serial Quad I/O™ (SQI™) Series Flash The device features a 6-wire 4-bit I/O interface that allows Low power, high performance operation with low pin count pack. The SST26VF032B/032BA also supports full command set compatibility for legacy Serial Peripheral Interface (SPI) protocols. System Design Using SQI Flash devices take up less board space, ultimately lowering system cost. All members of the 26 series, SQI series are manufactured Utilizes proprietary high-performance CMOS SuperFlash® technology. Split gate cell design and thick oxide tunnel injectors for better reliability and manufacturability compared to alternatives. SST26VF032B/032BA significantly improves performance and reliability while reducing power consumption. These Device is written (programmed or erased) using a single power supply 2.3-3.6V. The total energy consumed is Apply voltage, current and application time. therefore For any given voltage range, SuperFlash technology uses less current to program and have shorter erase times, The total energy consumed during any erase or program operation is lower than alternative flash technologies. Two configurations are available when ordering.

2. Feature

    1. Single voltage read and write operations:

        - 2.7V-3.6V or 2.3V-3.6V

    2. Serial Interface Architecture:

        - Nibble multiplexed I/O with SPI-like serial Command structure

        - Mode 0 and Mode 3

        - x1/x2/x4 Serial Peripheral Interface (SPI) protocol

    3. High-speed clock frequency:

        - 2.7V-3.6V: 104 MHz max

        - 2.3V-3.6V: 80 MHz max

    4. Burst Mode:

        - Continuous linear bursts

        - 8/16/32/64 byte linear burst with wraparound

    5. Outstanding reliability:

        - Endurance: 100,000 cycles (minimum)

        - Over 100 years of data retention

    6. Low power consumption:

        - Active read current: 15 mA (typical @ 104 MHz)

        - Standby current: 15 µA (typ)

    7. Fast Erase Time:

        - Sector/Block Erase: 18 ms (typ), 25 ms (maximum)

        - Chip Erase: 35 ms (typical), 50 ms (maximum)

    8. Pager program:

        - 256 bytes per page in x1 or x4 mode

    9. End of write detection:

        - Software polls the BUSY bit in the STATUS register

  10. Flexible Erase Capability:

        - Uniform 4 KB sectors

        - Four 8-KByte top and bottom parameter stacks yuan

        - A 32 KB top and bottom overlay block

        - Uniform 64 KB overlay block

  11. Write pending:

        - Suspend program or erase operations to access another block/sector

  12. Software reset (RST) mode

  13. Software write protection:

        - Single block write protection with permanent function Locking capability

        - 64 KB blocks, two 32 KB blocks and Eight 8 KB parameter blocks

        - Top and bottom 8 KB read protection parameter block

  14. Security ID:

        - One Time Programmable (OTP) 2 KB, Security ID:

        - 64-bit unique factory pre-programmed identifier

        - User programmable area

  15. temperature range:

        - Industrial: -40°C to +85°C

        - Industrial Grade: -40°C to +105°C

        - Extended: -40°C to +125°C

  16. Automotive AEC-Q100 Grades 1, 2 and Third grade

  17. Available packages:

        - 8 Contact WDFN (6mm x 5mm)

        - 8-pin SOIJ (5.28mm)

        - 24 Ball TBGA (6mm x 8mm)

  18. All equipment is RoHS compliant

3. Pin configuration

4. Pin Description

5. SPI Dual I/O Read

The SPI Dual I/O Read (SDIOR) command supports frequencies up to 80 MHz. Start SDIOR by executing an 8-bit command, BBH. The device then switches to 2-bit I/O mode with address bits A[23:0] followed by the set modeconfiguration bits M[7:0]. CE# must remain active low during SPI dual I/O reads. For SPI Dual I/O Read Sequence. After setting the mode configuration bits, the SST26VF032B/032BA outputs the data from the specified address location. The device continues to transmit data through all address outputs until terminated by a low-to-high transition on CE#. The internal address pointer is automatically incremented until the memory is at its maximum. When the address is reached, the address pointer returns to the beginning of the address space. Set Mode Configuration bits M[7:0] to indicate if the next instruction cycle is another SPI Dual I/O Read command. When M[7:0] = AXH, the device expects the next sequential instruction to be another SDIOR command BBH and does not require the opcode to be entered again. The host can set the next SDIOR cycle by driving CE# low, then sending a two-bit wide input for address A[23:0], followed by setting the mode configuration bits M[7:0]. After setting the Mode Configuration bit, the device starts at the specified address location for output data. Unlimited location access. When M[7:0] is any value other than AXH, the next instruction the device expects to start is a command indication. To reset/exit the setup mode configuration, execute the reset Quad I/O command FFH.