STM32L476JGY6UTR

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1. Describe

The STM32L476JGY6UTR devices are ultra-low-power microcontrollers based on the high-performance Arm® Cortex®-M4 32-bit RISC core, operating at up to 80 MHz. The Cortex-M4 core features floating- point unit (FPU) single-precision, supporting all Arm® single-precision data processing instructions and data types. It also implements a complete set of DSP instructions and a memory protection unit (MPU) to enhance application security. STM32L476xx devices embed high-speed memory (up to 1 MB flash, up to 128 KB SRAM), flexible external memory controller (FSMC) for static memory (for devices with 100 or more pins package), quad SPI flash interface (applies to all packages) ) and various enhanced I/Os and peripherals connected to two APB buses, two AHB buses, and a 32-bit multi-AHB bus matrix. STM32L476xx devices embed multiple protection mechanisms for embedded flash and SRAM: read protection, write protection, proprietary code readout Protection and Firewall. These devices provide up to three fast 12-bit ADCs (5 Msps), two comparators, two op amps, two DAC channels, an internal voltage reference buffer, a low power RTC, two general purpose 32-bit timing Timers, two 16 bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. These devices support four digital filters for external Sigma Delta Modulators (DFSDM). Additionally, up to 24 capacitive sensing channels are available. The device also embeds a Integrated LCD driver 8x40 or 4x44 with internal boost converter. Several independent power supplies are supported: analog independent power supply inputs for ADC, DAC, OPAMP, and comparators, a dedicated 3.3 V power supply input for USB, and up to 14 I/Os that can be independently powered to 1.08 V. The VBAT input allows backup of the RTC and backup registers. When connected to an external SMPS, a dedicated VDD12 supply can be used to bypass the internal LDO regulator. The STM32L476JGY6UTR family is available in six packages ranging from 64-pin to 144-pin packages.

2. Features

    1. Ultra-low-power with FlexPowerControl

        – 1.71 V to 3.6 V power supply

        – -40 °C to 85/105/125 °C temperature range

        – 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers

        – 30 nA Shutdown mode (5 wakeup pins)

        – 120 nA Standby mode (5 wakeup pins)

        – 420nA Standby mode with RTC

        – 1.1 µA Stop 2 mode, 1.4 µA with RTC

        – 100 µA/MHz run mode (LDO Mode)

        – 39 μA/MHz run mode (@3.3 V SMPS Mode)

        – Batch acquisition mode (BAM)

        – 4 µs wakeup from Stop mode

        – Brown out reset (BOR)

        – Interconnect matrix

    2. Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions

    3. Performance benchmark

        – 1.25 DMIPS/MHz (Drystone 2.1)

        – 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz)

    4. Energy benchmark

        – 294 ULPMark™ CP score

        – 106 ULPMark™ PP score

    5. Clock Sources

        – 4 to 48 MHz crystal oscillator

        – 32 kHz crystal oscillator for RTC (LSE)

        – Internal 16 MHz factory-trimmed RC (±1%)

        – Internal low-power 32 kHz RC (±5%)

        – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy)

        – 3 PLLs for system clock, USB, audio, ADC

    6. Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V

    7. RTC with HW calendar, alarms and calibration

    8. LCD 8× 40 or 4× 44 with step-up converter

    9. Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors

  10. 16x timers: 2x 16-bit advanced motor-control, 2x 32-bit and 5x 16-bit general purpose, 2x 16- bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer

  11. Memories

        – Up to 1 MB Flash, 2 banks read-whilewrite, proprietary code readout protection

        – Up to 128 KB of SRAM including 32 KB with hardware parity check

        – External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories

        – Quad SPI memory interface

  12. 4x digital filters for sigma delta modulator

  13. Rich analog peripherals (independent supply)

        – 3x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps

        – 2x 12-bit DAC output channels, low-power sample and hold

        – 2x operational amplifiers with built-in PGA

        – 2x ultra-low-power comparators

  14. 20x communication interfaces

        – USB OTG 2.0 full-speed, LPM and BCD

        – 2x SAIs (serial audio interface)

        – 3x I2C FM+(1 Mbit/s), SMBus/PMBus

        – 5x USARTs (ISO 7816, LIN, IrDA, modem)

        – 1x LPUART (Stop 2 wake-up)

        – 3x SPIs (and 1x Quad SPI)

        – CAN (2.0B Active) and SDMMC interface

        – SWPMI single wire protocol master I/F

        – IRTIM (Infrared interface)

  15. 14-channel DMA controller

  16. True random number generator

  17. CRC calculation unit, 96-bit unique ID

  18. Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ 

  19. All packages are ECOPACK2® compliant

3. Analog to digital converter

    1. 12-bit native resolution, with built-in calibration

    2. 5.33 Msps maximum conversion rate with full resolution

        – Down to 18.75 ns sampling time

        – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution)

    3. Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3.

    4. 5 internal channels: internal reference voltage, temperature sensor, VBAT/3,DAC1_OUT1 and DAC1_OUT2.

    5. One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply

    6. Single-ended and differential mode inputs

    7. Low-power design

        – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed)

        – Dual clock domain architecture: ADC speed independent from CPU frequency

    8. Highly versatile digital interface

        – Single-shot or continuous/discontinuous sequencer-based scan mode: 

           2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

        – Handles two ADC converters for dual mode operation (simultaneous or interleaved sampling modes)

        – Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals

        – Results stored into 3 data register or in RAM with DMA controller support

        – Data pre-processing: left/right alignment and per channel offset compensation

        – Built-in oversampling unit for enhanced SNR

        – Channel-wise programmable sampling time

        – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers

        – Hardware assistant to prepare the context of the injected channels to allow fast context switching

4. Digital to analog converter

    1. Up to two DAC output channels

    2. 8-bit or 12-bit output mode

    3. Buffer offset calibration (factory and user trimming)

    4. Left or right data alignment in 12-bit mode

    5. Synchronized update capability

    6. Noise-wave generation

    7. Triangular-wave generation

    8. Dual DAC channel independent or simultaneous conversions

    9. DMA capability for each channel

  10. External triggers for conversion

  11. Sample and hold low-power mode, with internal or external capacitor

5. General purpose input/output

Each GPIO pin can be configured by software as an output (push-pull or open-drain), an input (with or without pull-up or pull-down), or a peripheral alternate function. Most GPIO pins are shared with digital or analog alternate functions. Fast I/O switching is possible due to their mapping on the AHB2 bus. If desired, the I/O alternate function configuration can be locked in a specific order to avoid spurious writes to the I/O registers.

6. Advanced Communication Interface

    1. Three I2C

    2. Three SPIs

    3. Three USARTs, two UARTs and one low power UART.

    4. Two SAI (Serial Audio Interface)

    5. SDMMC

    6. a jar

    7. One USB OTG full speed

    8. One SWPMI (Single Wire Protocol Master)