W25Q32JVSSIQ

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1. Describe

The W25Q32JVSSIQ (32M bit) serial flash memory provides a storage solution for systems with limited space, pins, and power. The 25Q series offers flexibility and performance far beyond ordinary seria flash memory devices. They are ideal for mapping code to RAM, executing code and storing directly from dual/quad SPI (XIP) Voice, text and data. The device is powered by a 2.7V to 3.6V power supply, and its current consumption is as low as 1μA when the power is off. The W25Q32JV array is organized into 16,384 programmable pages, each page has 256 bytes. Up to 256 bytes can be programmed at a time. The page can be erased in 16 groups (4KB sector erase), 128 groups (32KB block erase), 256 groups (64KB block erase) or the entire chip (chip erase). W25Q32JV has 1,024 erasable sectors and 64 erasable blocks respectively. The small 4KB sector provides greater flexibility for applications that require data and parameter storage. W25Q32JV supports standard serial peripheral interface (SPI), high performance dual/quad output and dual/quad I/O SPI: serial clock, chip select, serial data I/O0 (DI), I/O1 (DO) , I/O2 and I/O3. Supports SPI clock frequency up to 133MHz. When using the fast read dual/quad I/O instruction, the dual I/O equivalent clock frequency is 266MHz (133MHz x 2), and the quad I/O equivalent clock frequency is 532MHz (133MHz x 4). These transfer rates can outperform standard asynchronous 8-bit and 16-bit parallel flash memories remember. In addition, the device supports JEDEC standard manufacturer and device ID and SFDP registers, a 64-bit unique serial number, and three 256-byte security registers.

2. Feature

    1. New SpiFlash memory series

        – W25Q32JV: 32M bits/4M bytes

        – Standard SPI: CLK, /CS, DI, DO

        – Dual SPI: CLK, /CS, IO0, IO1,

        – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

        – Software and hardware reset (1)

    2. The highest performance serial flash

        – 133MHz single, dual/quad SPI clock

        – 266/532MHz equivalent dual/quad SPI

        – 66MB/S continuous data transfer rate

        – minute. 100K program erase cycle per sector

        – Data retention for more than 20 years

    3. Efficient "continuous reading"

        – Use 8/16/32/64 byte line feed to read continuously

        – Addressing memory only requires 8 clocks

        – Allow true XIP (execute in place) operations

        – Better than X16 parallel flash

    4. Low power consumption, wide temperature range

        – Single 2.7V to 3.6V power supply

        – <1µA power down (typical value)

        – -40°C to +85°C operating range

        – -40°C to +105°C operating range

    5. Flexible architecture with 4KB sectors

        – Unified sector/block erase (4K/32K/64K bytes)

        – Program 1 to 256 bytes per programmable page

        – Erase/program pause and resume

    6. Advanced security features

        – Software and hardware write protection

        – Special OTP protection (2)

        – Top/bottom, complementary array protection

        – Single block/sector array protection

        – 64-bit unique ID for each device

        – Discoverable parameter (SFDP) register

        – 3X256 byte security register

        – Volatile and non-volatile status register bits

    7. Space-saving packaging

        – 8-pin SOIC/VSOP 150/208-mil

        – 16-pin SOIC 300-mil

        – 8-pin PDIP 300-mil

        – 8-pad WSON 6x5-mm/8x6-mm

        – 8-pad XSON 4x4-mm

        – 24 ball TFBGA 8x6 mm (6x4/5x5 ball array)

        – Contact Winbond to get KGD and other options

3. Pin configuration

4. Pin description

5. Pin function

1. Chip Select (/CS)

    The SPI chip select (/CS) pin enables and disables device operation. When /CS is high, the device is deselected, and the serial data output (DO, or IO0, IO1, IO2, IO3) pins are in high impedance. when Cancel the selection, and the device power consumption will be at the standby level, unless an internal erase, program, or write status register cycle is in progress. When /CS is pulled low, the device will be selected and the power supply Consumption will increase to the active level, and instructions can be written to the device and data can be read from the device. After power-on, /CS must change from high to low before accepting new commands. The /CS input must track the VCC power supply level during power-up and power-down (see "Write Protection" and Figure 58). If needed, a pull-up resistor on the /CS pin can be used to accomplish this.

2. Serial data input, output and IO (DI, DO and IO0, IO1, IO2, IO3)

    W25Q32JV supports standard SPI, dual SPI and quad SPI operation. Standard SPI commands use the unidirectional DI (input) pin to write commands, addresses, or data serially to the device on the rising edge of the serial clock (CLK) input pin. Standard SPI also uses a unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instructions use bidirectional IO pins to serially write instructions, addresses, or data to the device on the rising edge of CLK, and read data or status from the device on the falling edge of CLK. The Quad SPI instruction needs to set the non-volatile Quad Enable bit (QE) in Status Register 2. When QE=1, the /WP pin becomes IO2, and the /HOLD pin becomes IO3.

3. Write protection (/WP)

     The write protect (/WP) tatus Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. 

4. Serial Clock (CLK)

     The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.